Add waveform dumping

test/test_arith.ml

@@ -8,6 +8,10 @@ let () =
   let module Sim = Cyclesim.With_interface(Arith.I)(Arith.O) in
   let sim = Sim.create (Arith.create scope) in
 
+  let vcd_file = "./test_arith.vcd" in
+  let oc = Stdio.Out_channel.create vcd_file in
+  let sim = Vcd.wrap oc sim in
+
   let inputs = Cyclesim.inputs sim in
   let outputs = Cyclesim.outputs ~clock_edge:Before sim in
 
@@ -1186,6 +1190,9 @@ Stdio.printf "=== End Montgomery Debug Test ===\n\n";
   Stdio.printf "=== Test Summary ===\n";
   Stdio.printf "Passed: %d/%d\n" passed total;
 
+  Stdio.Out_channel.close oc;
+  Stdio.printf "Saved waveform to %s\n" vcd_file;
+
   if passed = total then begin
     Stdio.printf "\n";
     Stdio.printf "███████╗██╗   ██╗ ██████╗ ██████╗███████╗███████╗███████╗\n";
@@ -1198,4 +1205,4 @@ Stdio.printf "=== End Montgomery Debug Test ===\n\n";
   end else begin
     Stdio.printf "\n✗ Some tests failed - review above for details\n";
     failwith "checks failed";
-  end
+  end

test/test_ecdsa.ml

@@ -8,6 +8,10 @@ let () =
   let module Sim = Cyclesim.With_interface(Ecdsa.I)(Ecdsa.O) in
   let sim = Sim.create (Ecdsa.create scope) in
 
+  let vcd_file = "./test_ecdsa.vcd" in
+  let oc = Stdio.Out_channel.create vcd_file in
+  let sim = Vcd.wrap oc sim in
+
   let inputs = Cyclesim.inputs sim in
   let outputs = Cyclesim.outputs sim in
 
@@ -338,6 +342,9 @@ let () =
   Stdio.printf "=== Test Summary ===\n";
   Stdio.printf "Passed: %d/%d\n" passed total;
 
+  Stdio.Out_channel.close oc;
+  Stdio.printf "Saved waveform to %s\n" vcd_file;
+
   if passed = total then begin
     Stdio.printf "\n";
     Stdio.printf "███████╗██╗   ██╗ ██████╗ ██████╗███████╗███████╗███████╗\n";
@@ -350,4 +357,4 @@ let () =
   end else begin
     Stdio.printf "\n✗ Some tests failed - review above for details\n";
     failwith "checks failed";
-  end
+  end

test/test_mod_add.ml

@@ -13,6 +13,10 @@ let test () =
   let module Sim = Cyclesim.With_interface(Mod_add.ModAdd.I)(Mod_add.ModAdd.O) in
   let sim = Sim.create (Mod_add.ModAdd.create scope) in
 
+  let vcd_file = "./test_mod_add.vcd" in
+  let oc = Stdio.Out_channel.create vcd_file in
+  let sim = Vcd.wrap oc sim in
+
   let inputs = Cyclesim.inputs sim in
   let outputs = Cyclesim.outputs ~clock_edge:Before sim in
 
@@ -132,6 +136,9 @@ let test () =
   Stdio.printf "=== Test Summary ===\n";
   Stdio.printf "Passed: %d/%d\n" passed total;
 
+  Stdio.Out_channel.close oc;
+  Stdio.printf "Saved waveform to %s\n" vcd_file;
+
   if passed = total then begin
     Stdio.printf "\n✓ All tests passed!\n";
   end else begin

test/test_mod_inv.ml

@@ -45,6 +45,10 @@ let test () =
   let module Sim = Cyclesim.With_interface(ModInvWithModAdd.I)(ModInvWithModAdd.O) in
   let sim = Sim.create (ModInvWithModAdd.create scope) in
 
+  let vcd_file = "./test_mod_inv.vcd" in
+  let oc = Stdio.Out_channel.create vcd_file in
+  let sim = Vcd.wrap oc sim in
+
   let inputs = Cyclesim.inputs sim in
   let outputs = Cyclesim.outputs sim in
 
@@ -220,6 +224,9 @@ let test () =
   Stdio.printf "=== Test Summary ===\n";
   Stdio.printf "Passed: %d/%d\n" passed total;
 
+  Stdio.Out_channel.close oc;
+  Stdio.printf "Saved waveform to %s\n" vcd_file;
+
   if passed = total then begin
     Stdio.printf "\n";
     Stdio.printf "███████╗██╗   ██╗ ██████╗ ██████╗███████╗███████╗███████╗\n";

test/test_mod_mul.ml

@@ -41,6 +41,10 @@ let test () =
   let module Sim = Cyclesim.With_interface(ModMulWithModAdd.I)(ModMulWithModAdd.O) in
   let sim = Sim.create (ModMulWithModAdd.create scope) in
 
+  let vcd_file = "./test_mod_mul.vcd" in
+  let oc = Stdio.Out_channel.create vcd_file in
+  let sim = Vcd.wrap oc sim in
+
   let inputs = Cyclesim.inputs sim in
   let outputs = Cyclesim.outputs sim in
 
@@ -173,6 +177,9 @@ let test () =
   Stdio.printf "=== Test Summary ===\n";
   Stdio.printf "Passed: %d/%d\n" passed total;
 
+  Stdio.Out_channel.close oc;
+  Stdio.printf "Saved waveform to %s\n" vcd_file;
+
   if passed = total then begin
     Stdio.printf "\n";
     Stdio.printf "███████╗██╗   ██╗ ██████╗ ██████╗███████╗███████╗███████╗\n";

test/test_security_block.ml

@@ -12,8 +12,12 @@ let () =
   let module Sim = Cyclesim.With_interface(Security_block.I)(Security_block.O) in
   let sim = Sim.create (Security_block.create scope) in
 
+  let vcd_file = "./test_security_block.vcd" in
+  let oc = Stdio.Out_channel.create vcd_file in
+  let sim = Vcd.wrap oc sim in
+
   let inputs = Cyclesim.inputs sim in
-  let outputs = Cyclesim.outputs sim in
+  let outputs = Cyclesim.outputs ~clock_edge:Before sim in
 
   let prime_n = Arith.Config.prime_n in
 
@@ -199,11 +203,21 @@ let () =
   in
 
   let do_workload ~a ~b =
+    (* Drive inputs *)
     inputs.workload_valid := Bits.vdd;
     inputs.int8_a := int8_to_bits a;
     inputs.int8_b := int8_to_bits b;
+
+    (* wait for input sampling (1st cycle) *)
     Cyclesim.cycle sim;
+
+    (* deassert valid *)
     inputs.workload_valid := Bits.gnd;
+
+    (* wait for output generation (2nd cycle) *)
+    Cyclesim.cycle sim;
+
+    (* sample and return the outputs *)
     let result = bits_to_int8 !(outputs.int8_result) in
     let valid = Bits.to_bool !(outputs.result_valid) in
     (result, valid)
@@ -656,6 +670,9 @@ let () =
   Stdio.printf "=== Test Summary ===\n";
   Stdio.printf "Passed: %d/%d\n" passed total;
 
+  Stdio.Out_channel.close oc;
+  Stdio.printf "Saved waveform to %s\n" vcd_file;
+
   if passed = total then begin
     Stdio.printf "\n";
     Stdio.printf "███████╗██╗   ██╗ ██████╗ ██████╗███████╗███████╗███████╗\n";