Feature/verilog port#12

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peter-drotos wants to merge 6 commits intomainfrom

feature/verilog_port

Commits on Mar 24, 2026

Setup Verilog flow with dummy files
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Commits on Mar 25, 2026

ported mod_add and created TB
peter-drotos
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Commits on Mar 27, 2026

ported mod_mul, mod_inv and arith
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Commits on Mar 31, 2026

ported ecdsa
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Commits on Apr 1, 2026

ported top-level
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Commits on Apr 3, 2026

full review of the porting
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