Verilog Flattening

This project is an upgraded version of FlattenRTL, designed to more efficiently flatten Verilog designs and generate a more readable Verilog file by leveraging Verilator.
The tool parses Verilog code and outputs a flattened, human-readable version of the design.
Additionally, eq_check is provided for equivalence checking, which requires Formality to be installed.

⚠️ Important: Due to certain optimizations performed by Verilator (such as signal merging or pruning), some DFFs may not match between the original and the flattened design during equivalence checking.
However, all primary inputs (PIs) and primary outputs (POs) are guaranteed to match.
If you need to perform equivalence checking, please set `SEPARATE_ASSIGN_FOR_EQ_CHECK` to `True` in `src/main.py`.

This is an alpha version: the codebase still contains many uncleaned comments and debug fragments
If the output Verilog is too long or not well-formatted, you can enable the sv2v formatter, or disable it to keep the raw structure. 


Requirements:
- Verilator: Currently only supports version 5.043. Please run `install_verilator.sh` before using the tool.
- sv2v (optional)

python src/main.py --help
usage: main.py [-h] (--file FILE | --filelist FILELIST) --top TOP -o OUTPUT [--force]

Verilog AST to Source Code Generator

options:
  -h, --help            show this help message and exit
  --file FILE           Input Verilog file path
  --filelist FILELIST   Path to a file containing a list of Verilog files
  --top TOP             Top module name
  -o OUTPUT, --output OUTPUT
                        Output Verilog file path
  --force               Force overwrite output file if it exists