GitHub - MuhammadUsman3506/Verilog_Basic_RTL_Module_Trainning: basic verilog module training

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
INST_TAMPLATES		INST_TAMPLATES
adder		adder
arithmatic_operations		arithmatic_operations
decoder		decoder
demuxes/demux_1_to_2		demuxes/demux_1_to_2
encoder		encoder
gates		gates
muxes		muxes
subtractor		subtractor