Universal_Shift_Register

designed Universal Shift Register Using Verilog

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
8_to_1_mux.v		8_to_1_mux.v
D_FF.v		D_FF.v
README.md		README.md
Universal_Shift_reg_tb.v		Universal_Shift_reg_tb.v
Universal_Shift_reg_wave.png		Universal_Shift_reg_wave.png
Universal_shift_reg.v		Universal_shift_reg.v

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