CalculatorVHDL

Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.

Full project report

Full report is available here

Unit testing before combining files and component unless you are certainly sure that it will work as intended.

Name		Name	Last commit message	Last commit date
Latest commit History 30 Commits
.qsys_edit		.qsys_edit
.gitattributes		.gitattributes
.gitignore		.gitignore
BCDto7Segment.vhd		BCDto7Segment.vhd
BinaryAdderAndSubtractor.vhd		BinaryAdderAndSubtractor.vhd
BinaryDivider.vhd		BinaryDivider.vhd
BinaryMultiplier.vhd		BinaryMultiplier.vhd
BinaryToBCDConverterADD.vhd		BinaryToBCDConverterADD.vhd
BinaryToBCDConverterDIV.vhd		BinaryToBCDConverterDIV.vhd
BinaryToBCDConverterMUL.vhd		BinaryToBCDConverterMUL.vhd
BinaryToBCDConverterPreviewA.vhd		BinaryToBCDConverterPreviewA.vhd
BinaryToBCDConverterPreviewB.vhd		BinaryToBCDConverterPreviewB.vhd
BinaryToBCDConverterPreviewOperator.vhd		BinaryToBCDConverterPreviewOperator.vhd
BinaryToBCDConverterSUB.vhd		BinaryToBCDConverterSUB.vhd
CalculatorVHDL.qpf		CalculatorVHDL.qpf
CalculatorVHDL.qsf		CalculatorVHDL.qsf
CalculatorVHDL.vhd		CalculatorVHDL.vhd
CalculatorVHDL_assignment_defaults.qdf		CalculatorVHDL_assignment_defaults.qdf
CalculatorVHDL_description.txt		CalculatorVHDL_description.txt
FSM.vhd		FSM.vhd
Fulladder.vhd		Fulladder.vhd
MUX18to3_Remainder.vhd		MUX18to3_Remainder.vhd
MUX18to3_Result.vhd		MUX18to3_Result.vhd
OperatorSelector.vhd		OperatorSelector.vhd
README.md		README.md
SignDetector.vhd		SignDetector.vhd
SignDetectorPreview.vhd		SignDetectorPreview.vhd
Waveform.vwf		Waveform.vwf
Waveform1.vwf		Waveform1.vwf
Waveform2.vwf		Waveform2.vwf
cr_ie_info.json		cr_ie_info.json
vhdl_ls.toml		vhdl_ls.toml