[Update] : Merged commits from main branch to release branch#3170
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bkhodiax merged 8 commits intorelease/2.14.0from Jun 2, 2025
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[Update] : Merged commits from main branch to release branch#3170bkhodiax merged 8 commits intorelease/2.14.0from
bkhodiax merged 8 commits intorelease/2.14.0from
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The user clock frequency configuration protocol varies across devices. Move the Agilex 7 and Stratix 10 configuration sequences out of fpga_user_clk.c and into a new protocol-specific file. Signed-off-by: Michael Adler <michael.adler@altera.com>
Agilex 5 uses a new masked read-modify-write interface in hardware. OFS defines a new general interface (type 2) that allows software to set the address, value and mask for an IOPLL register to update. At the moment it is used only by Agilex 5. The M, N, C0 and C1 values for Agilex 5 and 7 are the same. Signed-off-by: Michael Adler <michael.adler@altera.com>
PEP 427 [https://peps.python.org/pep-0427/] specifies that dots in the project name are normalized to underscores in the wheel filename for compatibility and to avoid issues with filesystems and tooling.
Agilex 5 user clock reset was unreliable with the previous timeout. Signed-off-by: Michael Adler <michael.adler@altera.com>
…3167) Replaced function assertEquals with assertEqual as it deprecated.
nahidhassan-intel
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Jun 2, 2025
michael-adler
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Jun 2, 2025
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Merged commits from main branch to release branch