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tests/posix_semaphore: add (lack of) fe310 timer accuracy workaround#11377

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kaspar030:tests_posix_semaphore_fe310_fix
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tests/posix_semaphore: add (lack of) fe310 timer accuracy workaround#11377
kaspar030 wants to merge 1 commit intoRIOT-OS:masterfrom
kaspar030:tests_posix_semaphore_fe310_fix

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On hifive1, the test runs slightly longer than the default allows. This is probably caused by the board using a 32kHz timer as base for xtimer. This PR adds a workaround (allow up to 250usec/sec too long) only for the FE310 cpu.

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#11041

@kaspar030 kaspar030 added Area: tests Area: tests and testing framework CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms labels Apr 11, 2019
@kaspar030 kaspar030 requested a review from miri64 April 11, 2019 13:37
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Superceded by #11467.

@kaspar030 kaspar030 closed this May 6, 2019
@kaspar030 kaspar030 deleted the tests_posix_semaphore_fe310_fix branch July 19, 2019 18:41
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Area: tests Area: tests and testing framework CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms

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