At the center of an embedded system lies the processor, which is crucial as the main functional unit responsible for processing instructions and data. In embedded systems the most widely used processors are reduced instruction set computers, or RISC for short. Examples of such processors are the ARM and MIPS architectures.

A recent development has been the emergence of the RISC-V instruction set architecture (ISA) which has many big technology companies sponsoring the project. RISC-V stands out from previous architectures with its open-source nature, scalability and flexibility, making it a promising choice for future implementations in embedded systems.

Within the realm of RISC-V architecture, the implementation of custom processors presents an exciting opportunity for exploration and innovation. This project covers the design and implementation of a RISC-V processor. Exploring computer architecture, instruction sets and hardware implementation.

The primary objective of this project involves the design and implementation of a RISC-V processor for FPGA using SystemVerilog. It follows a systematic approach, starting from a basic 5 stage pipeline and gradually increasing the number of functions and supported instructions in the design through iterative stages of simulation, synthesis, and physical implementation on FPGA.