verilog_practice

This repository contains my complete hands-on journey into Verilog HDL — from beginner to advanced level.
All code is written, simulated, and tested using tools like Icarus Verilog, GTKWave, Yosys, and EDAPlayground.

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🚀 How to Run Simulations Locally

1. Install tools:

   • Icarus Verilog
   • GTKWave
   • (Optional) Yosys

2. Compile and simulate:

   iverilog -o and_sim and_gate.v and_gate_test.v
   vvp and_sim
   

3. View waveform:

   gtkwave and_wave.vcd

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🌐 Online Simulation

You can also run and visualize this project using EDAPlayground:

• Select Icarus Verilog as the simulator
• Use GTKWave viewer
• Paste your code in the left (testbench) and right (design) panes

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📌 Goals

• ✅ From logic gates → FSMs → RTL design → Synthesizable modules
• ✅ Include testbenches, waveforms, and synthesis outputs
• ✅ Organized and beginner-friendly

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👨‍💻 Author

• Name: Rahul (@Rahulpro963)
• Focus: VLSI, digital logic, and hardware design

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📜 License

This repo is for learning purposes. You're free to fork, use, or contribute!