DCDCv9-3r1.3

Important update for all v9-3r users!

An issue with Q11 was found. The exact cause of it's failure is still not fully understood.
Here what's currently known:

• Q11 became permantently conductive when the DCDC operated at above 570V from a HV battery during enabling or applying load
• this failure appeared 2 times on the same DCDC within 3 Days at above 570V but never in the weeks before below 550V
• currently this failure cannot be reproduced with a HV power supply and has not appeared during tests, not even at 605V
• new measurements show, that at 600V input a slight overvoltage between Q11's Drain-Source appear on the rising edge, resulting in 620V seen by the FET. Although the FET is rated for 650V, it is arguably not optimal.
• starting at around 575 V the U_ds rise and fall times drastically increased from 30 ns (575V) to around 60 ns (600V) on Q11 and Q10
  
  Q10 Mesurement, Yellow: Drain-Source Voltage, Purple: Gate-Source Voltage
• Gate Drive Voltage remains the same
• Previous version (v9-2) operates mostly on the same halfbridge design, but 10 Ohm gate resistors instead of 4.7 Ohm. The resonant circuit is also a bit different. The v9-2 was used as a temporary replacement for v9-3 and did not suffer any failures under similar conditions
• this issue did not occur to another teams's v9-3 replica (yet?)

Suspected cause (best guesses)

Gate Resistors
At first the lower value gate resistors where suspected to cause higher overvoltage due to faster switching. However measurements show, that it only slightly influcences the overvoltage at lower voltages. At 600V input the Drain-Source voltage was 616V at 10 Ohm compared to 619V at 4.7 Ohm. So this might be not the cause.

Dead-Time
The weird increase of rise- and fall times above 575V raised the question, whether the dead time was too short. The current dead time was measured at 113 ns (between the outputs of the UCC25600). Increasing it to 180 ns did nothing but increase the current consumption by ~0.3 mA at 500 V (no load). The wave forms and rise/fall times remained the same. The waveforms also did not hint (afaik) to anything that could resemble a halfbidge short due to too low dead time.

Q10 Mesurement, Yellow: Drain-Source Voltage, Red: Drain-Souce Current measured with a rogowski coil (might be not very accurate, just a test)

Hard switching
Although the LLC topology is known for it's soft switching, this is not entirely true depending on input voltage and load.
The primary current waveform transitions with higher input voltage and lower load from a sine to a triangle. This means, that the FETs are switching while current is still conducted, thus being hard switched. This might put load on the FETs while switching, which may result in longer switching times (not sure about this) and higher losses. However, higher losses have not been thermally measured.
Also when enabled, the softstart will begin switching at around 350 kHz. This can also cause hard switching at enable or self restart (e.g. due to overload) → Might be a main cause.

All of the above
As the pieces come together, it could be the following picture:
During turn on, the softstart will operate at higher frquencies, causing hard switching and prolonged switching times. The dead time might then be too short, causing a half bridge short (but why only Highside FET damaged?). It is also possible, that the smaller value on the gate resistors are causing the FETs to be switched even harder, causing more thermal stress/EMI/overvoltage. This might be also an issue for the Bootstrap (Diode) - however UVLO of the gate driver should avoid such casualties, but would explain why only the highside FET seems to be affected.

Solution

As the mystery is not fully solved, the following changes were made as a first attempt:

• Changed gate resistors R56/R58 from 4.7 Ohm to 10 Ohm
• Increased dead time to 180 ns (can be measured beween Pin 8 and 5 at U12, measure the time at 0V)
• ordered FETs with higher breakdown Voltage: 750V and 1200V
  Note: The 750V has lower switching losses than the 1200V version. I will go with the 750V version first.

For now, the first tests will be conducted with the current 650V FETs but with altered dead time and 10 Ohm gate resistors.
If there are any news, I will update this text. Also join the discussion in the Issues-Section. I appreciate every idea!

Changes

Documentation

Change	Page
Changed “Vocabulary and list of abbreviations” to “Glossary of Abbreviations”	5
Distinguished between insulation and isolation, other small wording improvements	misc.

Build Guide

Change	Page
Improvement of the description of the secondary windings and their connections.	16
Added fault if enable switch resistance is too high.	29
Added fault when the secondary windings are swapped.	30
Extended note on IR thermometer Measurement inaccuracy	31
Added note about not using 24 V on the output for testing due to the control loop shutting down the converter (which must happen - but is not useful for tests)	28/29

PCB

• Changed Gate Resistors R56/R58 from 4.7 Ohm to 10 Ohm

DCDCv9-3r1.2

• Updated all Docs, for details see Revision History (new) on last page of each document:

Documentation:

Change	Page
Added update regards magnetic flux calculation	33
Added note in case of error message in LTSpice and missing Solver	53/54
Revision history added for future changes	63
Improved translation and formatting of miscellaneous words	misc.

Build Guide:

Change	Page
Replaced “instructions” by ‘Build Guide’ in the first sentence of the second section for better clarity	6
Specified “Specify Layer Sequence”	8
Improved wording in the caption of the screenshot, replaced “current sign” by “voltage sign”, swapped values R67 and R68 for 400 V (does not change anything electrically, but looks nicer)	39
Added Revision History for future changes	47
Improved translation and formatting of miscellaneous words	misc.

Table and Datasheet:

• Added storage time and voltage after this time for C_start1

Miscellaneous:

• added STEP files in addition to the STL for Transformer parts

• fixed components on Mouser_BOM_for_PCBA despite being already placed on the PCBA:

  • D3,D4,D5,D6,D7 (LED Green)
  • C5,C33,C46 (10 µF 0805)
  • added UCC25600 for PCBA

• included improvements on LTspice Simulations

• Changed Mounting Holes from 2.9 mm to 3.0 mm.
  Although 2.9 mm was a nice fit for M3 screws, increasing it a bit will help against manufacturing tolerances.
  Note: The footprint originated from a M2.5 Footprint. Despite changing the diameter, the old name remained in the footprint title until now.
  Rules note: T 10.1.2 does not apply (Minimum M4), als the DCDC is not part of any primary structure. However, if somebody really needs M4, it is totally possible to increase the hole size by drilling - there is enough distance between the hole and traces. Just make sure that any screw heads are not shorting anything. The use of M4 pan head screws might therefore not be possible.

DCDCv9-3r1.1

Increased spacings on coil formers. Width changed from 22 mm to 26 resulting in 2 mm more on each side. This increases creepage distance to at least 4 mm (realistically it's more than 6 mm) to better comply with EV 4.3.6 (FSG Rules 2025 v1.1) and adding more margin of error in case of looser coil winding.
Center split width on the primary coil former was decreased from 0.9 to 0.8 mm to allow 0.05 mm more space for the primary

If you've already made the coil formers with an older version, capton tape between the primary and secondary coil formers can be used to increase creepage and clearance distances.

Note: I'm not sure, if EV 4.3.6 is even applicable for enamelled HF-litz wire. The transformer/coils pass the 1 min. 3 kV RMS AC Isolation test without conformal coating with the old coil formers.

Blue: Old Coil former

DCDCv9-3r1

This release fixes small clearance issues:

1. Increased the spacing below the gate driver from 0.3 mm to 0.6 mm, as the IPC 2221 does not provide for spacing between the inner and outer layers.
2. The same applies to the trace below the resonant capacitors (also moved capacitors to the left).

3. R54 Pad 1 footprint distance has been increased from 0.2 mm to 1.2 mm. Simulations have shown that this pad can reach up to 400 V to GND, so that at least 0.8 mm is required. However, it was increased to 1.2 mm to be safe in the event of a voltage surge.

Q&A

Q: I've already ordered PCBs for the DCDCv9-3r, should I order new ones?
A: The fixed issues 1. and 2. are afaik best practices, but there might be little to no change in likelihood of a failure in this area. For issue 3. the resistor R54 does limit the current to such a small value, that even in an event of a breakdown just 36 mW will dissapear, which would be no issue for the resistor. However, the additional current sensing might not work anymore and lead to overload of the SR-MOSFETs when large uncharged capacitors are connected. The overcurrent protection would then rely soley on F1 - which is permittable. In doubt, remove Pad 1 of R54 on the PCB and connect R54 to C39 directly.
I would give those fixes a re-order rating of 3 out of 5. If you are willing to make the R54 fix I would rate it just 1.5 out of 5.

DCDCv9-3r

Dear Reader,
this is the first public release of the DC/DC-Converter Project.
The unexpected complexity of some problems led a delay in the open source release of around 2 years. (sorry)
That being said, there are still some areas that could be improved, but those improvements (like efficiency)
are not relevant to the successful operation of the converter and would only cause further delay.
Feel free to reach out in the GitHub Discussions if you like to improve in those areas (they are described in the documentation document).
Also some smaller topics are left out in the documentation and will be added later.
Since I know no one willing to proof-read over 100 Pages of documentation, build guide and datasheet, they certainly contain errors for sure and might feel a bit stiff. If you are willing to check some of the pages for mistakes (factual, logical but also spelling and grammatical errors), please let me know in the GitHub Discussions.

Please note, that I am in the examination phase until end of February 2025.
If there are any questions, please create a new discussion on GitHub. I’ll try my best to answer them in my time spare.

I wish you much success in building your own DCDCv9-3r !

Kind Regards
Rootthecause / Liv