SoC-Lab-Final

Project Description

This project have four branch

1. main
   • Implement UART FIFO workload
2. 3_exp
   • SDRAM-based FIR, Qsort, Matmul workload
3. base
   • Lab 6 implementation - baseline
   • https://github.com/Sheng08/SoC-Lab-lab6
4. opt
   • This is the branch of UART FIFO development, you can ignore this branch