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Function regex issue

on hold

Status: Open.

#64 In TheClams/SystemVerilog;

· sxu55 opened on Mar 27, 2023

Highlight function being edited in module hierarchy

Status: Open.

#48 In TheClams/SystemVerilog;

· jbshaler opened on Feb 22, 2022

Several useful features for Verilog / SystemVerilog

Status: Open.

#37 In TheClams/SystemVerilog;

· Fynjisx26 opened on Aug 16, 2021

LSP Support?

Status: Open.

#36 In TheClams/SystemVerilog;

· ghost opened on Aug 1, 2021

Reindenting typedefs indents poorly

Status: Open.

#26 In TheClams/SystemVerilog;

· DeeeeLAN opened on Feb 16, 2021

Local function variables conflict with aliased module variables

on hold

Status: Open.

#7 In TheClams/SystemVerilog;

· timLinscott opened on Mar 4, 2020

method completion based on class ancestors?

Status: Open.

#2 In TheClams/SystemVerilog;

· DeeeeLAN opened on Sep 27, 2019