AXI4-Stream UART TX/RX for FPGA devices
BAUD_RATE- TX/RX Baud rateCLK_FREQ- Input clock frequency
Note: The baud rate must be at least 4 times the clock frequency.
clk_i- Clockrst_i- Resetuart_tx_o- UART TXuart_rx_i- UART RX
m_axis_rx_tdata[7:0]m_axis_rx_tvalid
s_axis_tx_tdata[7:0]s_axis_tx_tvalids_axis_tx_tready
The module has been functionally verified using cocotb and GHDL.
To run the testbench, install the dependencies in the requirements file and run python tb/main.py.
On a Gowin GW2A family FPGA this synthesizes to ~58 LUTs at ~297 MHz (C8/I7 grade), the lower the ratio between the clock frequency and baud rate, the lower the utilization and higher max frequency. Thus, higher baud rates are usually preferred. For the clock domain crossing a double flop synchronizer has been used with the appropriate synthesis attributes to disable optimizations by Gowin synthesis.
An example UART loopback project is included in the fpga folder. It is designed to be used with a Sipeed Tang Primer 20k FPGA board but should be easily adaptable to other boards as well.