feat: update project tt_um_silicon_art from dxa4481/tiny

Commit: e08acbdd390ec1ca30e70ccb866eb4769f4e0702
Workflow: https://github.com/dxa4481/tiny/actions/runs/19998166051

Author: TinyTapeoutBot

projects/tt_um_silicon_art/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout main bbd9aa18",
+  "app": "custom_gds action",
   "repo": "https://github.com/dxa4481/tiny",
-  "commit": "f6ba2671c44df1ac6487a752b118a1c84ac78726",
-  "workflow_url": "https://github.com/dxa4481/tiny/actions/runs/19954450932",
+  "commit": "e08acbdd390ec1ca30e70ccb866eb4769f4e0702",
+  "workflow_url": "https://github.com/dxa4481/tiny/actions/runs/19998166051",
   "project_id": 3497,
   "sort_id": 1764832851934
 }

projects/tt_um_silicon_art/docs/info.md

@@ -11,7 +11,7 @@ The design includes:
 2. A decorative border frame around the design
 3. All required TinyTapeout pins properly defined on Metal4.pin layer
 4. Power pins (VPWR, VGND) on TopMetal1.pin layer
-5. A minimal Verilog stub that passes inputs through with an XOR pattern
+5. A minimal Verilog stub with all outputs tied to ground
 
 **Important DRC note:** Art uses `.drawing` layers (datatype 0) which are the only fabricated layers in TinyTapeout's IHP whitelist. All geometry meets DRC requirements:
 - Pixel art: ~7.88 µm pixels (min: 0.20 µm) ✅
@@ -25,13 +25,11 @@ The design fits in the 202.08 × 154.98 µm tile area (TinyTapeout IHP 1x1 tile)
 
 The functional logic is minimal (just for TinyTapeout compatibility):
 
-1. Apply any 8-bit input pattern to `ui_in[7:0]`
-2. The output `uo_out[7:0]` will be the input XOR'd with 0xAA
+1. All digital outputs (`uo_out[7:0]`) are tied to ground (0x00)
+2. All bidirectional outputs (`uio_out[7:0]`) are also grounded
+3. Bidirectional pins are configured as inputs (`uio_oe = 0x00`)
 
-For example:
-- Input: 0x00 → Output: 0xAA
-- Input: 0xFF → Output: 0x55
-- Input: 0xAA → Output: 0x00
+The design maintains connections to all input pins internally to satisfy synthesis requirements, but outputs remain at logic 0 regardless of input values.
 
 ## External hardware
 

projects/tt_um_silicon_art/pdk.json

@@ -1,7 +1,3 @@
 {
-  "FLOW_NAME": "LibreLane",
-  "FLOW_VERSION": "3.0.0.dev44",
-  "PDK": "ihp-sg13g2",
-  "PDK_SOURCE": "IHP-Open-PDK",
-  "PDK_VERSION": "cb7daaa8901016cf7c5d272dfa322c41f024931f"
-}
+  "PDK": "ihp-sg13g2"
+}