feat: update project tt_um_aksp_mbist_mbisr from adityapundir1985/tt_um_aksp_mbist_mbisr

Commit: 94fb5aa8865fabb74fac5f77e0feda1e236115b6
Workflow: https://github.com/adityapundir1985/tt_um_aksp_mbist_mbisr/actions/runs/19987226194

Author: TinyTapeoutBot

projects/tt_um_aksp_mbist_mbisr/LICENSE

@@ -0,0 +1,3 @@
+Apache License
+Version 2.0, January 2004
+http://www.apache.org/licenses/

projects/tt_um_aksp_mbist_mbisr/commit_id.json

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+{
+  "app": "Tiny Tapeout main deda2f4f",
+  "repo": "https://github.com/adityapundir1985/tt_um_aksp_mbist_mbisr",
+  "commit": "94fb5aa8865fabb74fac5f77e0feda1e236115b6",
+  "workflow_url": "https://github.com/adityapundir1985/tt_um_aksp_mbist_mbisr/actions/runs/19987226194",
+  "project_id": 3498,
+  "sort_id": 1765017369039
+}

projects/tt_um_aksp_mbist_mbisr/docs/info.md

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+# MBIST with MBISR Memory Test and Repair System
+
+## How it works
+
+This project implements a Memory Built-In Self-Test (MBIST) controller with integrated Memory Built-In Self-Repair (MBISR) capabilities. The system automatically tests an embedded 256×8-bit SRAM memory and can repair faulty cells on-the-fly.
+
+### Key Components:
+
+1. **MBIST Controller** (`mbist_marchc_controller.v`):
+   - Implements March C- algorithm (simplified variant)
+   - Tests memory with pattern: {↕(w0); ↑(r0,w1); ↓(r1,w0); ↑(r0)}
+   - Reports per-address failures via `fail_valid` and `fail_addr` signals
+
+2. **MBISR Controller** (`mbisr_controller.v`):
+   - Content-Addressable Memory (CAM) style repair logic
+   - Supports up to 16 repair entries
+   - Automatically remaps faulty addresses to spare memory region (0xF0-0xFF)
+   - Transparent to user - faulty addresses are automatically redirected
+
+3. **Memory Module** (`memory.v`):
+   - 256×8-bit synchronous SRAM
+   - Configurable address and data widths
+   - Supports read/write operations
+
+4. **Integration Top** (`top.v`):
+   - Connects MBIST, MBISR, and memory modules
+   - Manages test execution and repair coordination
+
+### Operation Flow:
+
+1. **Initialization**: Memory is cleared to zero on reset
+2. **Test Start**: User asserts `START` signal
+3. **March C- Execution**: MBIST runs through 4 march elements:
+   - Write 0 ascending (↕w0)
+   - Read 0, Write 1 ascending (↑r0,w1)
+   - Read 1, Write 0 descending (↓r1,w0)
+   - Read 0 ascending verification (↑r0)
+4. **Fault Detection**: Any mismatched read triggers failure reporting
+5. **Automatic Repair**: MBISR records faulty addresses and remaps to spares
+6. **Completion**: `DONE` signal asserted, `FAIL` indicates if faults were found
+
+## How to test
+
+### Test Interface:
+
+**Inputs:**
+- `clk`: System clock (any frequency up to 1MHz)
+- `rst_n`: Active-low reset (assert to initialize)
+- `START` (ui[0]): Begin MBIST test (pulse high)
+
+**Outputs:**
+- `DONE` (uo[0]): Test completion indicator (high when finished)
+- `FAIL` (uo[1]): Fault detection indicator (high if any faults found)
+
+### Test Procedure:
+
+1. **Apply clock signal** (typically 1-10MHz)
+2. **Release reset** (set `rst_n = 1`)
+3. **Start test** (pulse `START` high for at least 1 clock cycle)
+4. **Monitor outputs**:
+   - `DONE = 0`, `FAIL = 0`: Test in progress
+   - `DONE = 1`, `FAIL = 0`: Test passed (memory intact)
+   - `DONE = 1`, `FAIL = 1`: Test completed with faults (repairs applied)
+5. **Repeat test** as needed (system resets between runs)
+
+### Simulation Testing:
+
+```bash
+cd test
+make          # Run RTL simulation
+make GATES=yes # Run gate-level simulation

projects/tt_um_aksp_mbist_mbisr/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "MBIST + MBISR Built-In Memory Test & Repair"      # Project title
+  author:       "Dr Aditya Kumar Singh Pundir, Dr Pallavi Singh"      # Your name
+  discord:      "dradityapundir"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "Memory Built-In Self-Test (March C-) and Built-In Self-Repair with CAM-based faulty address remapping."      # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     10000000       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_aksp_mbist_mbisr"
+
+  # List your project's source files here.
+  # Source files must be in ./src and you must list each source file separately, one per line.
+  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
+  source_files:
+    - "tt_um_aksp_mbist_mbisr.v"
+    - "top.v"
+    - "mbist_marchc_controller.v"
+    - "mbisr_controller.v"
+    - "memory.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+# This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
+pinout:
+  # Inputs
+  ui[0]: "START"          # MBIST start signal (active high)
+  ui[1]: ""               # Unused
+  ui[2]: ""               # Unused
+  ui[3]: ""               # Unused
+  ui[4]: ""               # Unused
+  ui[5]: ""               # Unused
+  ui[6]: ""               # Unused
+  ui[7]: ""               # Unused
+
+  # Outputs
+  uo[0]: "DONE"           # MBIST completion status (active high)
+  uo[1]: "FAIL"           # MBIST failure status (active high if fault detected)
+  uo[2]: ""               # Unused
+  uo[3]: ""               # Unused
+  uo[4]: ""               # Unused
+  uo[5]: ""               # Unused
+  uo[6]: ""               # Unused
+  uo[7]: ""               # Unused
+
+  # Bidirectional pins
+  uio[0]: ""              # Unused (configured as input)
+  uio[1]: ""              # Unused (configured as input)
+  uio[2]: ""              # Unused (configured as input)
+  uio[3]: ""              # Unused (configured as input)
+  uio[4]: ""              # Unused (configured as input)
+  uio[5]: ""              # Unused (configured as input)
+  uio[6]: ""              # Unused (configured as input)
+  uio[7]: ""              # Unused (configured as input)
+
+# Do not change!
+yaml_version: 6

projects/tt_um_aksp_mbist_mbisr/pdk.json

@@ -0,0 +1,7 @@
+{
+  "FLOW_NAME": "LibreLane",
+  "FLOW_VERSION": "3.0.0.dev44",
+  "PDK": "ihp-sg13g2",
+  "PDK_SOURCE": "IHP-Open-PDK",
+  "PDK_VERSION": "cb7daaa8901016cf7c5d272dfa322c41f024931f"
+}

projects/tt_um_aksp_mbist_mbisr/stats/metrics.csv

@@ -0,0 +1,186 @@
+Metric,Value
+design__lint_error__count,0
+design__lint_timing_construct__count,0
+design__lint_warning__count,5
+design__inferred_latch__count,0
+design__instance__count,2351
+design__instance__area,28941.5
+design__instance_unmapped__count,0
+synthesis__check_error__count,0
+design__max_slew_violation__count__corner:nom_fast_1p32V_m40C,0
+design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C,1
+design__max_cap_violation__count__corner:nom_fast_1p32V_m40C,0
+power__internal__total,0.0005084325675852597
+power__switching__total,0.0001777306606527418
+power__leakage__total,0.0000012110145917176851
+power__total,0.0006873742095194757
+clock__skew__worst_hold__corner:nom_fast_1p32V_m40C,-0.2580389308596379
+clock__skew__worst_setup__corner:nom_fast_1p32V_m40C,0.2582579223574388
+timing__hold__ws__corner:nom_fast_1p32V_m40C,0.13052218009172442
+timing__setup__ws__corner:nom_fast_1p32V_m40C,14.776633668246921
+timing__hold__tns__corner:nom_fast_1p32V_m40C,0.0
+timing__setup__tns__corner:nom_fast_1p32V_m40C,0.0
+timing__hold__wns__corner:nom_fast_1p32V_m40C,0
+timing__setup__wns__corner:nom_fast_1p32V_m40C,0.0
+timing__hold_vio__count__corner:nom_fast_1p32V_m40C,0
+timing__hold_r2r__ws__corner:nom_fast_1p32V_m40C,0.130522
+timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C,0
+timing__setup_vio__count__corner:nom_fast_1p32V_m40C,0
+timing__setup_r2r__ws__corner:nom_fast_1p32V_m40C,18.313389
+timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C,0
+design__max_slew_violation__count__corner:nom_slow_1p08V_125C,0
+design__max_fanout_violation__count__corner:nom_slow_1p08V_125C,1
+design__max_cap_violation__count__corner:nom_slow_1p08V_125C,0
+clock__skew__worst_hold__corner:nom_slow_1p08V_125C,-0.2605281619735503
+clock__skew__worst_setup__corner:nom_slow_1p08V_125C,0.26091313181822673
+timing__hold__ws__corner:nom_slow_1p08V_125C,0.6614113888235399
+timing__setup__ws__corner:nom_slow_1p08V_125C,13.406190315102398
+timing__hold__tns__corner:nom_slow_1p08V_125C,0.0
+timing__setup__tns__corner:nom_slow_1p08V_125C,0.0
+timing__hold__wns__corner:nom_slow_1p08V_125C,0
+timing__setup__wns__corner:nom_slow_1p08V_125C,0.0
+timing__hold_vio__count__corner:nom_slow_1p08V_125C,0
+timing__hold_r2r__ws__corner:nom_slow_1p08V_125C,0.661411
+timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C,0
+timing__setup_vio__count__corner:nom_slow_1p08V_125C,0
+timing__setup_r2r__ws__corner:nom_slow_1p08V_125C,16.347385
+timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C,0
+design__max_slew_violation__count__corner:nom_typ_1p20V_25C,0
+design__max_fanout_violation__count__corner:nom_typ_1p20V_25C,1
+design__max_cap_violation__count__corner:nom_typ_1p20V_25C,0
+clock__skew__worst_hold__corner:nom_typ_1p20V_25C,-0.2587981568965002
+clock__skew__worst_setup__corner:nom_typ_1p20V_25C,0.25900801680966523
+timing__hold__ws__corner:nom_typ_1p20V_25C,0.3243774785035836
+timing__setup__ws__corner:nom_typ_1p20V_25C,14.291236154547047
+timing__hold__tns__corner:nom_typ_1p20V_25C,0.0
+timing__setup__tns__corner:nom_typ_1p20V_25C,0.0
+timing__hold__wns__corner:nom_typ_1p20V_25C,0
+timing__setup__wns__corner:nom_typ_1p20V_25C,0.0
+timing__hold_vio__count__corner:nom_typ_1p20V_25C,0
+timing__hold_r2r__ws__corner:nom_typ_1p20V_25C,0.324377
+timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C,0
+timing__setup_vio__count__corner:nom_typ_1p20V_25C,0
+timing__setup_r2r__ws__corner:nom_typ_1p20V_25C,17.596252
+timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C,0
+design__max_slew_violation__count,0
+design__max_fanout_violation__count,1
+design__max_cap_violation__count,0
+clock__skew__worst_hold,-0.2580389308596379
+clock__skew__worst_setup,0.2582579223574388
+timing__hold__ws,0.13052218009172442
+timing__setup__ws,13.406190315102398
+timing__hold__tns,0.0
+timing__setup__tns,0.0
+timing__hold__wns,0
+timing__setup__wns,0.0
+timing__hold_vio__count,0
+timing__hold_r2r__ws,0.130522
+timing__hold_r2r_vio__count,0
+timing__setup_vio__count,0
+timing__setup_r2r__ws,16.347385
+timing__setup_r2r_vio__count,0
+design__die__bbox,0.0 0.0 202.08 154.98
+design__core__bbox,2.88 3.78 199.2 151.2
+design__io,45
+design__die__area,31318.4
+design__core__area,28941.5
+design__instance__count__stdcell,713
+design__instance__area__stdcell,11470.6
+design__instance__count__macros,0
+design__instance__area__macros,0
+design__instance__count__padcells,0
+design__instance__area__padcells,0
+design__instance__count__cover,0
+design__instance__area__cover,0
+design__instance__utilization,0.396339
+design__instance__utilization__stdcell,0.396339
+design__rows,39
+design__rows:CoreSite,39
+design__sites,15951
+design__sites:CoreSite,15951
+design__instance__count__class:buffer,2
+design__instance__area__class:buffer,14.5152
+design__instance__count__class:inverter,20
+design__instance__area__class:inverter,114.307
+design__instance__count__class:sequential_cell,82
+design__instance__area__class:sequential_cell,4078.77
+design__instance__count__class:multi_input_combinational_cell,398
+design__instance__area__class:multi_input_combinational_cell,3730.41
+flow__warnings__count,1
+flow__errors__count,0
+design__power_grid_violation__count__net:VPWR,0
+design__power_grid_violation__count__net:VGND,0
+design__power_grid_violation__count,0
+design__instance__count__class:timing_repair_buffer,180
+design__instance__area__class:timing_repair_buffer,3055.45
+timing__drv__floating__nets,0
+timing__drv__floating__pins,0
+design__instance__displacement__total,0
+design__instance__displacement__mean,0
+design__instance__displacement__max,0
+route__wirelength__estimated,15177.2
+design__violations,0
+design__instance__count__class:clock_buffer,17
+design__instance__area__class:clock_buffer,400.982
+design__instance__count__class:clock_inverter,14
+design__instance__area__class:clock_inverter,76.2048
+design__instance__count__setup_buffer,0
+design__instance__count__hold_buffer,147
+global_route__vias,4627
+global_route__wirelength,26239
+antenna__violating__nets,0
+antenna__violating__pins,0
+route__antenna_violation__count,0
+antenna_diodes_count,0
+route__net,718
+route__net__special,2
+route__drc_errors__iter:0,293
+route__wirelength__iter:0,16736
+route__drc_errors__iter:1,53
+route__wirelength__iter:1,16457
+route__drc_errors__iter:2,43
+route__wirelength__iter:2,16459
+route__drc_errors__iter:3,0
+route__wirelength__iter:3,16463
+route__drc_errors,0
+route__wirelength,16463
+route__vias,4086
+route__vias__singlecut,4086
+route__vias__multicut,0
+design__disconnected_pin__count,16
+design__critical_disconnected_pin__count,0
+route__wirelength__max,369.55
+design__instance__count__class:fill_cell,1638
+design__instance__area__class:fill_cell,17470.9
+timing__unannotated_net__count__corner:nom_fast_1p32V_m40C,30
+timing__unannotated_net_filtered__count__corner:nom_fast_1p32V_m40C,0
+timing__unannotated_net__count__corner:nom_slow_1p08V_125C,30
+timing__unannotated_net_filtered__count__corner:nom_slow_1p08V_125C,0
+timing__unannotated_net__count__corner:nom_typ_1p20V_25C,30
+timing__unannotated_net_filtered__count__corner:nom_typ_1p20V_25C,0
+timing__unannotated_net__count,30
+timing__unannotated_net_filtered__count,0
+design_powergrid__voltage__worst__net:VPWR__corner:nom_typ_1p20V_25C,1.1996
+design_powergrid__drop__average__net:VPWR__corner:nom_typ_1p20V_25C,1.19989
+design_powergrid__drop__worst__net:VPWR__corner:nom_typ_1p20V_25C,0.0004017
+design_powergrid__voltage__worst__net:VGND__corner:nom_typ_1p20V_25C,0.000304913
+design_powergrid__drop__average__net:VGND__corner:nom_typ_1p20V_25C,0.000097758
+design_powergrid__drop__worst__net:VGND__corner:nom_typ_1p20V_25C,0.000304913
+design_powergrid__voltage__worst,0.000304913
+design_powergrid__voltage__worst__net:VPWR,1.1996
+design_powergrid__drop__worst,0.0004017
+design_powergrid__drop__worst__net:VPWR,0.0004017
+design_powergrid__voltage__worst__net:VGND,0.000304913
+design_powergrid__drop__worst__net:VGND,0.000304913
+ir__voltage__worst,1.1999999999999999555910790149937383830547332763671875
+ir__drop__avg,0.000111000000000000001118029280267052172348485328257083892822265625
+ir__drop__worst,0.0004020000000000000135724764760425387066788971424102783203125
+magic__drc_error__count,0
+magic__illegal_overlap__count,0
+design__lvs_device_difference__count,0
+design__lvs_net_difference__count,0
+design__lvs_property_fail__count,0
+design__lvs_error__count,0
+design__lvs_unmatched_device__count,0
+design__lvs_unmatched_net__count,0
+design__lvs_unmatched_pin__count,0

projects/tt_um_aksp_mbist_mbisr/stats/synthesis-stats.txt

@@ -0,0 +1,45 @@
+163. Printing statistics.
+
+=== tt_um_aksp_mbist_mbisr ===
+
+   Number of wires:                486
+   Number of wire bits:            521
+   Number of public wires:          79
+   Number of public wire bits:     114
+   Number of ports:                  8
+   Number of port bits:             43
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                502
+     sg13g2_a21o_1                  10
+     sg13g2_a21oi_1                 22
+     sg13g2_a221oi_1                 4
+     sg13g2_a22oi_1                 26
+     sg13g2_and2_1                  11
+     sg13g2_and3_1                   5
+     sg13g2_and4_1                   2
+     sg13g2_buf_1                    2
+     sg13g2_dfrbpq_1                82
+     sg13g2_inv_1                   20
+     sg13g2_mux2_1                   3
+     sg13g2_nand2_1                 45
+     sg13g2_nand2b_1                11
+     sg13g2_nand3_1                 48
+     sg13g2_nand4_1                  2
+     sg13g2_nor2_1                  30
+     sg13g2_nor2b_1                  3
+     sg13g2_nor3_1                  11
+     sg13g2_nor4_1                   6
+     sg13g2_o21ai_1                 60
+     sg13g2_or2_1                   21
+     sg13g2_or3_1                    2
+     sg13g2_or4_1                    1
+     sg13g2_tiehi                   38
+     sg13g2_tielo                   22
+     sg13g2_xnor2_1                 10
+     sg13g2_xor2_1                   5
+
+   Chip area for module '\tt_um_aksp_mbist_mbisr': 7775.535600
+     of which used for sequential elements: 4017.081600 (51.66%)
+