This is a a Repository containing the design of a 16-bit CMOS full adder in 45nm cadence library
This project explores the design and analysis of a 16-bit CMOS full adder optimized for speed. A mirror adder-based ripple carry architecture was selected as the foundational design, which was then extended into a carry-select adder (CSLA) structure. The goal was to achieve a worst-case delay below 400 ps while analyzing power consumption and the power-delay product (PDP) under various operating conditions. Simulations were conducted to validate performance across different process corners and supply voltages, providing insights into the trade-offs between speed, power, and area.
- A customizable 16-bit carry-select adder using a mirror full adder topology.
- Achieves O(√n) delay for improved performance over traditional ripple carry adders.
- Simulated under multiple process corners (TT 27°C, FF -25°C, SS 85°C) to evaluate worst-case delay and power consumption.
- Analysis of power-delay product across different supply voltages to understand CMOS non-idealities.
- Suitable for high-speed applications where power and area constraints are secondary considerations.
- Move files to your local directory and launch using virtuoso and ADE XL.
- After running, customize accordingly.
We welcome contributions! If you'd like to contribute to this project, please follow the guidelines in CONTRIBUTING.md.
This project is licensed under the GNU General Public License v3.0 - see the LICENSE file for details.