vd100_platform

Vitis extensible platform for the VD100 AIE pipeline. Created from the XSA exported by the aie-pipeline Vivado block design.

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Overview

The platform wraps the hardware design (XSA) into a Vitis extensible platform (.xpfm) that the system project (vd100_ma_system_project) and AIE compiler use as their target.

It defines:

• The hardware specification (clocks, interrupts, memory, AXI interfaces)
• The software domain (Linux on A72, with sysroot and boot components)
• The extensible region where v++ inserts HLS kernels and AIE connections

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Platform File

vd100_platform/
└── export/
    └── vd100_platform/
        └── vd100_platform.xpfm    ← referenced by all downstream components

This path is hardcoded in:

• vd100-aie-ma-crossover/CMakeLists.txt (VITIS_PLATFORM_PATH)
• vd100_ma_system_project platform setting

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Creation

1. Export XSA from aie-pipeline Vivado project
2. In Vitis: File → New Platform Project
3. Select the exported XSA
4. Configure software domain:
   • OS: Linux
   • Processor: psu_cortexa72_0
   • Sysroot: point to Yocto SDK sysroot
5. Build the platform

Platform: vd100_platform
Device:   XCVE2302-SFVA784-1LP-E-S
PL clock: 100 MHz

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Downstream Usage

Component	How it uses this platform
vd100-aie-ma-crossover	AIE compiler target (--platform vd100_platform.xpfm)
mm2s / s2mm	HLS synthesis target
vd100_ma_system_project	v++ link and package target

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Notes

• Rebuild this platform whenever the aie-pipeline Vivado BD changes and a new XSA is exported.
• After rebuilding, clean and rebuild all downstream components (vd100-aie-ma-crossover, vd100_ma_system_project).
• The platform does not include the zocl DT node — that is handled separately by sdtgen set_dt_param -zocl enable in the vd100_dts step.