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Refactor CPU feature detection to use an explicit x86 whitelist#258

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ihb2032 wants to merge 6 commits intoalibaba:mainfrom
ihb2032:fix/non-x86-build
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Refactor CPU feature detection to use an explicit x86 whitelist#258
ihb2032 wants to merge 6 commits intoalibaba:mainfrom
ihb2032:fix/non-x86-build

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@ihb2032
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@ihb2032 ihb2032 commented Mar 24, 2026

Currently, cpu_features.cc assumes that any architecture that is not __ARM_ARCH must be an x86/x64 architecture and attempts to include <cpuid.h>. This causes fatal compilation errors on other architectures like RISC-V.
Changes Proposed
This PR refactors the preprocessor directives to use an explicit "whitelist" approach:

  • <cpuid.h> and x86-specific CPUID logic are now only compiled when x86_64 or i386 is explicitly defined or under MSVC for Windows.
  • All other architectures including ARM, RISC-V, etc. will safely fall back to the default initialization, allowing the project to compile successfully as generic C++ code.

Motivation
This resolves build failures on RISC-V environments and sets up a clean, safe foundation for potentially adding architecture-specific optimizations in the future.
closed #244

@ihb2032 ihb2032 requested a review from iaojnh as a code owner March 24, 2026 09:01
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@ihb2032 ihb2032 removed their assignment Mar 24, 2026
@zhourrr zhourrr requested a review from richyreachy April 14, 2026 03:15
@iaojnh iaojnh assigned richyreachy and iaojnh and unassigned iaojnh Apr 14, 2026
@richyreachy
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hi @ihb2032, as we noticed that RISC-V is available on github runner (#244), could you please setup a CI job on it along with this PR?

@ihb2032 ihb2032 requested a review from Cuiyus as a code owner April 15, 2026 10:59
…itelist

Currently, `cpu_features.cc` assumes any non-ARM architecture is x86/x64, which leads to a fatal missing `<cpuid.h>` error on architectures like RISC-V.
This commit refactors the preprocessor macros to explicitly whitelist x86 architectures (`__x86_64__`, `__i386__`, `_M_X64`, `_M_IX86`). All other architectures (RISC-V, ARM, etc.) will now safely fall back to the default zero-initialization, allowing cross-compilation to succeed.

Signed-off-by: ihb2032 <hebome@foxmail.com>
@ihb2032 ihb2032 force-pushed the fix/non-x86-build branch from 2192b65 to 061258b Compare April 15, 2026 11:11
Comment thread .github/workflows/03-macos-linux-build.yml
@ihb2032 ihb2032 force-pushed the fix/non-x86-build branch from 061258b to 5d725df Compare April 15, 2026 12:13
@ihb2032 ihb2032 requested a review from richyreachy April 15, 2026 12:14
Comment thread .github/workflows/03-macos-linux-build.yml
Introduce the RISC-V CI runner provided by the RISE project.
This enables automated testing and building for the RISC-V architecture.

Signed-off-by: ihb2032 <hebome@foxmail.com>
@ihb2032 ihb2032 force-pushed the fix/non-x86-build branch from 5d725df to 6040065 Compare April 15, 2026 12:51
@ihb2032 ihb2032 requested a review from richyreachy April 15, 2026 12:53
@richyreachy
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@ihb2032 please take a look at this error: https://github.com/alibaba/zvec/actions/runs/24500696519/job/71607486150

Seems the ci job can be brought up after Github App was setup.

Any problem, let me know.

@ihb2032
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ihb2032 commented Apr 16, 2026

Hi @richyreachy, thanks for pointing that out!

I checked the logs and the issue is that actions/setup-python currently doesn't provide a pre-built Python 3.10 binary for the riscv64 architecture on Ubuntu 24.04.

To fix this without breaking the other builds that share 03-macos-linux-build.yml, I've updated the workflow to conditionally use Python 3.12 only when inputs.platform == 'linux-riscv64', while keeping the rest on 3.10.

I've just pushed the fix, let's see if the CI turns green!

@ihb2032 ihb2032 force-pushed the fix/non-x86-build branch from 7549f02 to 777a546 Compare April 16, 2026 10:14
Signed-off-by: ihb2032 <hebome@foxmail.com>
@ihb2032 ihb2032 force-pushed the fix/non-x86-build branch from 777a546 to a0dbfc8 Compare April 16, 2026 11:34
ihb2032 added 2 commits April 16, 2026 21:12
Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
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[Feature]: Add CI pipeline for RISC-V / RVV

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