feat(plat/tc): enable MPAM functionality of L3 DSU cache

The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are accessed through utility bus of DSU that are memory mapped from
0x1_0000_1000.

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I2798181d599228e96dd4c0043a2ccd94668c7e20

Author: davidson-k

fdts/tc.dts

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -519,6 +519,15 @@
 		};
 	};
 
+	/*
+	 * L3 cache in the DSU is the Memory System Component (MSC)
+	 * The MPAM registers are accessed through utility bus in the DSU
+	 */
+	msc0 {
+		compatible = "arm,mpam-msc";
+		reg = <0x1 0x00010000 0x0 0x2000>;
+	};
+
 	ete0 {
 		compatible = "arm,embedded-trace-extension";
 		cpu = <&CPU0>;