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Releases: altera-fpga/gsrd-socfpga

25.3 PRO Release

13 Oct 19:18

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Release Information

Version: Release 25.3 PRO
Quartus Build/TAG: B109/QPDS25.3_REL_GSRD_PR
Release Date: October 10, 2025
Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10
Release Type: Major release/Binary release
Binary Release Path: http://releases.rocketboards.org/2025.10/

The source code and tools repositories with the current release branches or versions are shown next.

SW Component Release Repository Branch/Tag
Arm® Trusted Firmware https://github.com/altera-fpga/arm-trusted-firmware socfpga_v2.13.0/QPDS25.3_REL_GSRD_PR
U-Boot https://github.com/altera-fpga/u-boot-socfpga socfpga_v2025.07/QPDS25.3_REL_GSRD_PR
Linux kernel https://github.com/altera-fpga/linux-socfpga socfpga-6.12.33-lts/QPDS25.3_REL_GSRD_PR
Cyclone® V GHRD https://github.com/altera-fpga/cyclonev-ed-gsrd main/QPDS25.3_REL_GSRD_PR
Arria® 10 GHRD https://github.com/altera-fpga/arria10-ed-gsrd main/QPDS25.3_REL_GSRD_PR
Stratix® 10 GHRD https://github.com/altera-fpga/stratix10-ed-gsrd main/QPDS25.3_REL_GSRD_PR
Agilex™ 7 GHRD https://github.com/altera-fpga/agilex7f-ed-gsrd main/QPDS25.3_REL_GSRD_PR
Agilex™ 5 GHRD + GSRD 2.0 https://github.com/altera-fpga/agilex5e-ed-gsrd main/QPDS25.3_REL_GSRD_PR
Legacy GSRD https://github.com/altera-fpga/gsrd-socfpga Walnascar/QPDS25.3_REL_GSRD_PR
Reference Designs Sources https://github.com/altera-fpga/meta-intel-fpga-refdes Walnascar/QPDS25.3_REL_GSRD_PR
Reference Design Recipes (for Legacy GSRD) https://git.yoctoproject.org/meta-intel-fpga Walnascar/QPDS25.3_REL_GSRD_PR
Reference Design Recipes (for GSRD 2.0) https://github.com/altera-fpga/meta-altera-fpga Walnascar/QPDS25.3_REL_GSRD_PR
Yocto Project https://git.openembedded.org/meta-openembedded Walnascar
Reference Yocto Project https://git.yoctoproject.org/git/poky.git/ Walnascar
Baremetal Libraries https://github.com/altera-fpga/baremetal-drivers main/QPDS25.1_REL_GSRD_PR
ARM® Debugger https://www.intel.com/content/www/us/en/software-kit/846382/arm-development-studio-version-2024-1-for-intel-soc-fpga.html ARM DS 2024.1

HPS SW Compatibility

The information presented here shows the backward compatibility between the HPS Software Components and Quartus across different releases. The Validated text in a cell indicates that the combination of the HPS Software components with the versions indicated in the column was successfully validated, along with the Quartus version indicated in that row. The backwards and forward compatibility is read as indicated in the following figure:

compatibility

Stratix 10 HPS SW Compatibility table. Click the arrow at the left to show it.

Stratix 10 HPS SW Compatibility table

Quartus
Version
HPS
SW
Component
Rel 23.3 Rel 23.4 Rel 24.1 Rel 24.2 Rel 24.3 Rel 24.3.1 Rel 25.1 Rel 25.1.1 Rel 25.3
ATF 2.9.0 2.9.1 2.10.0 2.10.1 2.11.0 2.11.1 2.12.0 2.12.1 2.13.0
U-Boot 2023.04 2023.07 2023.10 2024.01 2024.04 2024.07 2025.01 2025.04 2025.07
Linux Kernel 6.1.38 6.1.55 6.1.68 6.6.22 6.6.37 6.6.51 6.12.11 6.12.19 6.12.33
Yocto 4.2.2
mickledore
4.3
nanbield
4.3
nanbield
5.0
scarthgap
5.0
scarthgap
5.1
styhead
5.1
styhead
5.2
walnascar
5.2
walnascar
21.4 $${\color{black}Validated}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$
22.1 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$
22.2 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$
22.3 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$
22.4 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$
23.1 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$
23.2 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{red}N/A}$$ $${\color{red}N/A}$$
23.3 $${\color{blue}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{red}N/A}$$
23.4 $${\color{black}Validated}$$ $${\color{blue}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$
24.1 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{blue}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$
24.2 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{blue}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$
24.3 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{blue}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$
25.1 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{blue}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$
25.1.1 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{blue}Validated}$$ $${\color{black}Validated}$$
25.3 $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{black}Validated}$$ $${\color{blue}Validated}$$

Note: The Stratix 10 device was not included as part of 24.3.1 Quartus release.

Agilex 7 HPS SW Compatibility table. Click the arrow at the left to show it. ...
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25.1.1 PRO Release

14 Aug 21:52

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Version: Release 25.1.1 PRO
Quartus Build/TAG: B125/QPDS25.1.1_REL_GSRD_PR
Release Date: Agust 10, 2025
Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10, Cyclone® V
Release Type: Major release/Binary release
Binary Release Path: http://releases.rocketboards.org/2025.08/

The source code and tools repositories with the current release branches or versions are shown next.

SW Component Release Repository Branch/Tag
Arm® Trusted Firmware https://github.com/altera-fpga/arm-trusted-firmware socfpga_v2.12.1/QPDS25.1.1_REL_GSRD_PR
U-Boot https://github.com/altera-fpga/u-boot-socfpga socfpga_v2025.04/QPDS25.1.1_REL_GSRD_PR
Linux kernel https://github.com/altera-fpga/linux-socfpga socfpga-6.12.19-lts/QPDS25.1.1_REL_GSRD_PR
Cyclone® V GHRD https://github.com/altera-fpga/cyclonev-ed-gsrd main/QPDS25.1.1_REL_GSRD_PR
Arria® 10 GHRD https://github.com/altera-fpga/arria10-ed-gsrd main/QPDS25.1.1_REL_GSRD_PR
Stratix® 10 GHRD https://github.com/altera-fpga/stratix10-ed-gsrd main/QPDS25.1.1_REL_GSRD_PR
Agilex™ 7 GHRD https://github.com/altera-fpga/agilex7f-ed-gsrd main/QPDS25.1.1_REL_GSRD_PR
Agilex™ 5 GHRD https://github.com/altera-fpga/agilex5e-ed-gsrd main/QPDS25.1.1_REL_GSRD_PR
Agilex™ 3 GHRD https://github.com/altera-fpga/agilex3c-ed-gsrd main/QPDS25.1.1_REL_GSRD_PR
GSRD https://github.com/altera-fpga/gsrd-socfpga Walnascar/QPDS25.1.1_REL_GSRD_PR
Reference Designs Sources https://github.com/altera-fpga/meta-intel-fpga-refdes Walnascar/QPDS25.1.1_REL_GSRD_PR
Reference Design Recipes https://git.yoctoproject.org/meta-intel-fpga Walnascar/QPDS25.1.1_REL_GSRD_PR
Yocto Project https://git.openembedded.org/meta-openembedded Walnascar
Reference Yocto Project https://git.yoctoproject.org/git/poky.git/ Walnascar
Baremetal Libraries https://github.com/altera-fpga/baremetal-drivers main/QPDS25.1_REL_GSRD_PR
ARM® Debugger arm-development-studio-version-2024-1-for-intel-soc-fpga ARM DS 2024.1
ARM® GCC Toolchain arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu 14.3.rel1

Features Released

Feature Description Component Affected Scope
Device/Board
HSD
(Internal Use)
Initial release to support Agilex 3 device. A new GSRD/GHRD for Agilex™ 3 FPGA C-Series Development Kit is provided. All Components Agilex 3 18039179745
14024417186
15017885834
Support the enabling if ECC in DDR in the Agilex 5 hardware designs. ECC is enabled by default in Agilex 5. U-Boot
ATF
Linux
GHRD
Agilex 5 22020850112
Released GSRD/GHRD for Agilex 7 F-Series Crypto DK-DEV-AGF0123FA using AGFD023R24C2E1VC(production device). The support of the DK-DEV-AGF027F1ES with AGFB027R24C2E2VR2 device (engineering samples) is no longer supported. GSRD
GHRD
Agilex 7 18028924210
18028924207
14024417186
GSRD (Linux and hardware) support of USB 3.1 in Agilex 5 GSRD
GHRD
Linux
Agilex 5 18025905328
18025954294
15013331340
Support of ATF to Linux Direct boot flow from eMMC Linux Agilex 5 15017459856
Removed NAND binaries from Agilex 5 ES devkit release. This will be reenable when PRQ devkit is ready. GSRD (meta-intel-fpga-refdes) Agilex 5 15018204509
Port New-FCS Client solution to Agilex7 platform Linux Agilex 7 16027204168

Fixed Issues

Issue Fixed Component Affected Scope
Device/Board
HSD
(Internal Use)
ATF to Linux Direct Flow fails to boot from SD Card with Agilex 5 25.1 GHRD due to incorrect power straps configuration in GHRD. Commit IDs: 4b8cc1c6e4 GHRD Agilex 5 14024688400
Add support of GHRD for Agilex 7 M-Series HBM Rev B (AGMF039R47A1E2VC). Commit IDs: d3e6e0258f GHRD Agilex 7 15017057883
Enable ECC in SDRAM by default in Agilex 5 GHRD. Commit IDs: d4ea118ec4 GHRD Agilex 5 15017350294
Unable to do read and write through f2h bridge after bridge enable in Agilex 7 M-Series. Commit IDs: e7d9e4c939 GHRD Agilex 7 15017689621
Failed to get IP during DHCP. Commit IDs: 4582ddc0e8f0ac56f5 GHRD Agilex 3 15017867041
Failed to get IP during DHCP. Revert EMAC clock frequency back to 250Mhz. Commit IDs: 5c8258de9b GHRD Agilex 5 15017904654
Timing constraints failed in TSN Config2 design. Commit IDs: 43106b6d25 GHRD Agilex 5 15017902187
Worng pin for usb31_phy clk in the hardware desing for Modular dev kit. Commit IDs: 105df75e1d GHRD Agilex 5 15017902281
Agilex 5 fails to ping from 2 dev kits connected back to back regardless these are able to get an IP address. Commit IDs: abe5a7e3f1 GHRD Agilex 5 15017936550
Unable to trigger LED in dev kit for Agilex 7 F-Series (2x F-Tile). Commit IDs: e667c37c3a GHRD Agilex 7 15018000122
Restructure Agilex 5 GHRD designs to solve build problems. Commit IDs: 4b5d3d9fa1 GHRD Agilex 5 18040154767
ATF to Linux Direct flow fails to provide network connectivity in Agilex 5. Incorrect settings in power straps in GHRD Commit IDs: 6e73f5023f GHRD Agilex 5 14024748396
Warm reset fails to be applied from Linux using the reboot command when using reboot=warm in the command line. Commit IDs: 410b93702a ATF Agilex 7
Stratix 10
14021922100
Enabling higher performance in work loads by DSU configuration. This includes disable sending data with clean evictions from DSU and disable broadcast atomics in DSU. Commit IDs: e250e4a07a ATF Agilex 5 14024591995
Prevent warnings in agilex5 platform from TF-A upstream branch. Commit IDs: bd822d5703 ATF Agilex 5 14024903111
Incorrect version is being reported by the rsu_client --log command after observing errors like application corruption or watchdog timer expiration. Commit IDs: c9bc871038 ATF Device agnostic 14025454721
Unable to individually reset a single secondary core from another ARM core (boot-core). This is done by turning-off and turning-off the seconday core from Linux echo > /sys/devices/system/cpu/cpuX/online. Commit IDs: 468ba0bbde ATF Agilex 5 15013500528
Support of ATF to Linux Direct boot flow from eMMC. Commit ID: 7337116f1f, cda27b58fd ATF Agilex 5 15017459856
Update of CPUECTLR_EL1 in ATF to Disable broadcast atomics & Disable sending clean evictions. Commit IDs: e250e4a07a ATF Agilex 5 15017524574
Add support to ATF to control the HPS request of QSPI ownership used for ATF to Linux direct flow. Commit IDs: 3d2fd855e0 ATF Agilex 5 15017581189
Failure in ATF DDR Size Retrieval Using IOSSM Mailbox During QSPI and SD Boot. Update iossm v2 enhancement. Commit IDs: 4ccd527c85 ATF Agilex 5 15017915961
Faiulre observed command sent by SD Host Controller after GHRD softphydiv update in ATF to Linux direct flow. When SDMMC sdmclk running at 200MHz setting the sdclk to 25MHz it fails, so setting the sdclk to 50MHz for SDMMC. Commit IDs: 7337116f1f ATF Agilex 5 15017916005
An unexpected DDR reset type value was observed in ATF to Linux Direct flow. Specifically, the reset type is reported as WARM when the board is freshly powered on, where COLD would be the expected value. Commit IDs: 9be0d26605 ATF Agilex 5 15017930348
After rebase of Linux 6.12: An arm-smmu prefetcher warning is observed due to MMU-500 errata; ATF patch is required to disable the prefetcher. Commit IDs: 0c466d9ad5 ATF Agilex 7 15018028852
Migrate in ATF RSU client from SiPSVC V1 to V3. Commit IDs: 3ab24e59f5, 50e0419a2f, f73ffc219ead ATF Agilex 3
Agilex 5
Agilex 7<Stratix 10
N5x
16026558537
Migrate miscelaneous utility functions from FCS driver to a common file. There are some utility functions to verify the 4/8/16/32 bytes data size alignment. Commit IDs: 4ef3f59717 ATF Device agnostic 16027084350
While executing the Get_digest command on the Agilex7 platform, we observed that the returned payload is zero du...
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25.1 PRO Release

18 Apr 00:52

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Release Information

Version: Release 25.1 PRO
Release Date: April 18, 2025
Device Affected: Agilex™ 5, Agilex™ 3, Agilex™ 7, Startix® 10, Arria® 10, Cyclone® V
Release Type: Mayor release/Binary release
Binary Release Path: http://releases.rocketboards.org/2025.04/

The source code and tools repositories with the current release branches or versions are shown next.

SW Component Release Repository Branch/Tag
Arm® Trusted Firmware https://github.com/altera-fpga/arm-trusted-firmware socfpga_v2.12.0/QPDS25.1_REL_GSRD_PR
U-Boot https://github.com/altera-fpga/u-boot-socfpga socfpga_v2025.01/QPDS25.1_REL_GSRD_PR
Linux kernel https://github.com/altera-fpga/linux-socfpga socfpga-6.12.11-lts/QPDS25.1_REL_GSRD_PR
Cyclone® V GHRD https://github.com/altera-fpga/cyclonev-ed-gsrd main/QPDS25.1_REL_GSRD_PR
Arria® 10 GHRD https://github.com/altera-fpga/arria10-ed-gsrd main/QPDS25.1_REL_GSRD_PR
Stratix® 10 GHRD https://github.com/altera-fpga/stratix10-ed-gsrd main/QPDS25.1_REL_GSRD_PR
Agilex™ 7 GHRD https://github.com/altera-fpga/agilex7f-ed-gsrd main/QPDS25.1_REL_GSRD_PR
Agilex™ 5 GHRD https://github.com/altera-fpga/agilex5e-ed-gsrd main/QPDS25.1_REL_GSRD_PR
GSRD https://github.com/altera-fpga/gsrd-socfpga styhead/QPDS25.1_REL_GSRD_PR
Reference Designs Sources https://github.com/altera-fpga/meta-intel-fpga-refdes styhead/QPDS25.1_REL_GSRD_PR
Reference Design Recipes https://git.yoctoproject.org/meta-intel-fpga styhead/QPDS25.1_REL_GSRD_PR
Yocto Project https://git.openembedded.org/meta-openembedded styhead
Reference Yocto Project https://git.yoctoproject.org/git/poky.git/ styhead
Baremetal Libraries https://github.com/altera-fpga/baremetal-drivers main/QPDS25.1_REL_GSRD_PR
ARM® Debugger https://www.intel.com/content/www/us/en/software-kit/846382/arm-development-studio-version-2024-1-for-intel-soc-fpga.html ARM DS 2024.1

Features Released

Feature Description Component Affected Scope
Device/Board
HSD
(Internal Use)
Discontinued building of GHRD for DK-SI-AGI027FA and DK-SI-AGI027FB development kits for Intel® Agilex™ I-Series Transceiver-SoC Development Kit (4x F-Tile). Example designs for eMMC boot for Agilex™ 7 and Stratix® 10 are no longer supported. GHRD Agilex™ 7 N/A
Enable/Disable Attestation or RSU use case based on new QSPI ownership selection. When SDM owns QSPI, attestation use case can be supported but not RSU use case. When HPS owns the QSPI, then RSU use case can be supported but not attestation. Linux Agilex™ 5 16026169736
Implement IEEE-1588v2.1 (2019) time stamp features in Ethernet TSN hard IP in addition to the 1588-v2 features. To meet the IEEE 60802 Industrial profile the IP should support 4 independent clock domains. Linux Agilex™ 5 15010611873
Create a Reference Designs demonstrating use of SDM crypto services API from FPGA and HPS as a separate modular add-on design that can builds seamlessly on top of the baseline Agilex 7 GSRD. This example should demonstrate access to crypto for SW load and other items: u-boot, ATF and Linux (to support VAB) GSRD Agilex™ 5 18025906520
Provide Linux kernel support query the ATF API version through a sysfs entry (/sys/kernel/fcs_sysfs/atf_version) Linux Agilex™ 5 18033846053
Create a series of example FPGA designs and software examples that interact with them. FPGA designs shall require no external pins or interfaces booting from SDM QSPI. Main objective is to enable users to answer the question, "how do I know that I've connected the hardware correctly and I'm accessing the CPU registers correctly? U-Boot
Linux
Agilex™ 5 14022178609
Complete support for remaining HPS peripherals, supported stacks and register settings. Extend support across bridges to FPGA soft IPs that have existing Nios HAL support with BSP. Baremetal Agilex™ 5 18039602242
Initial rebranding of eSW items from Intel to Altera (mainly Readme files this time). Also migrating GitHub repositories to atlera-fpga ATF
U-Boot
Linux
Device agnostic 14023606040
Migrate GHRD repositories to new GitHub layout on atlera-fpga GHRD Agilex™ 5
Agilex™ 7
S10
Arria® 10
Cyclone® V
14022046005
QSPI ownership is set from Quartus to decide if SDM will keep the ownership or if the ownership could be granted to the HPS. Quartus Agilex™ 5 14023286569
Support the SiPSVC V3 and new unified FCS client commands. ATF
Linux
Agilex™ 5
Agilex™ 7
S10
N5X
16026116212
16026116238
16026617451

Fixed Issues

Issue Fixed Component Affected Scope
Device/Board
HSD
(Internal Use)
Create a text file that containing the Quartuskit build number and also the git commit from the GHRD build for quick reference. Cron workflow needed to be updated. GHRD Agilex™ 5
Agilex™ 7
S10
Arria® 10
Cyclone® V
15017129225
15017295328
Need to have unique README file for each hardware design variant. GHRD Agilex™ 5 15017077043
Arria 10 GHRD ci is only producing sof and zip files. Also rbf and hps_isw_handoff is also require for GSRD. GHRD Arria® 10 15017264906
GTS IP (intel_srcss_gts) has been upgraded to v4.0.0 in 25.1. It has added one input and one output port to the IP. This caused an error in GHRD. GHRD Agilex™ 5 15017446027
U-Boot proper fails with "Synchronous Abort" when moving to socfpga_v2025.01. The issue is related to the GHRD for which the QSPI ownership is assigned by default to the SDM and needed to be changed to HPS. GHRD Agilex™ 5 15017445609
Missing .pmsf file to generate PR .rbfs. This were available in 24.3 but no longer available in 25.1. GHRD Agilex™ 7
S10
15017511373
Incorrect MPU clock rate is being reported in S10 as it's expected to be 1GHz but the actual clock rate returned is 1.2 GHz. This is a change in the GHRD from 25.1. The testcase needed to be updated to match the new clock frequency. GHRD S10 15017487322
Failing to trigger LED and response from interrupt switch in Agilex 7 I-Series devkit. Facing issue where LED unable to light up using both Linux application and webpage. Also the interrupt related to the DIP switch is not detected. However, for push button it was working ok. GHRD Agilex™ 7 15017568445
Timeout failure when applying Persona1 overlay. The error shown is FPGA manager "firmware:svc:fpga-mgr: timeout waiting for svc layer buffers". GHRD Agilex™ 7
S10
Arria® 10
15017600652
Integrate the SiPSVC V3 and new unified FCS client commands. Where FCS client can invoke SMC call asynchronously and can handle the response via callbacks(triggered on interrupt from the SDM) or via polling method from the client. This reduces latency in FCS calls. Commit IDs: 9fda9a29ba, 613daf8cb3, 8a7002e702. ATF Agilex™ 5
Agilex™ 7
S10
N5X
16026116212
16026759759
SIP SVC V3 in ATF did not taken care AES GCM related mailbox requirements in ATF. Commit IDs:59076985bc ATF Agilex 5 16026999724
16025999772
Agilex5 VAB CCERT address is not working as expected. The CCERT does not store in the allocated address. The pointer of the CCERT array is pointed to the wrong memory address. It shall point to the head of the array. Thus when send CCERT to SDM for authentication, the system is able to get the correct CCERT else it will return authentication failure. Commit IDs: c6b74311f76e. ATF Agilex™ 5 15017453043
Perform dynamic ddr memory data configuration based on hardware size when not configured in DTS. This is done based one the IO96B hardware size to initialize the memory size if user did not configure Memory range in DTS. Commit IDs: 4e4aeaad42. U-Boot Agilex™ 5 15016095242
Support full HPS boot of Agilex 7 M-Series REVB with HBM boot up HPS by removing all the FSBL HBM related handoff data. Commit IDs: e9b3afb938. U-Boot Agilex™ 7 15017340111
Migrate to the DDR IO mailbox cmd version 2: read only register and ECC Ring buffer. Commit IDs: d2d8ce15c5. U-Boot Agilex™ 5 15017211290
In the start.S file, the saved_args the default value is set to 0, but when run with ARM DS, we found the default value is some non-zero value. Commit IDs: 0abd2517c4. U-Boot Agilex™ 5 15017346429
Observed a U-Boot failure on NAND when using build 25.01. This issue was confirmed on both the mUDV and Devkit. However, when tested with the older build 24.07, U-Boot booted successfully. Error observed is: "Error code: DRAM: initcall failed at call 00000000802029a8 (err=-2)". Commit IDs: 3bb2808118. U-Boot Agilex™ 5 16026589523
Fixed compilation failure for Agilex 5 VAB with U-Boot socfpga_v2024.07 version (undefined reference to wdt_expire_now). Commit IDs: 353f8a4b3a. U-Boot Agilex™ 5 15017385094
...
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24.1 STD Release

21 Mar 22:13

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Intel FPGA HPS Embedded Software Release Notes

Version: Release 24.1 STD
Tag: QPDS24.1STD_REL_GSRD_PR
Release Date: March 21st, 2025
Devices Affected: Cyclone 5
Release Type: Major release/Binary release
Binary Release Path: https://releases.rocketboards.org/2025.03

Release Strategy

The HPS Embedded software releases for Intel FPGA devices are aligned with Quartus® releases and are scheduled as follows:

  • Quartus® Standard (STD): 1 release per year. This is a binary release.
  • Quartus® Pro (PRO): 4 releases per year, one each quarter. Some of these are Major release which affects most of the devices while Minor releases are released as needed and affect a few devices.

Embedded software releases can also be classified as Source code or Binary releases. A Source code release involves releasing only the source code in the software repositories. A Binary release consists of a source code release + pre-built binaries release that could be loaded directly into the development kits.

Note: To review the Release Notes prior 24.3.1 release please refer to the following link: https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease.

The source code and tools repositories with the current release branches or versions are shown next.

SW Component Release Repository Branch/Tag
Arm® Trusted Firmware https://github.com/altera-opensource/arm-trusted-firmware socfpga_v2.11.1/QPDS24.1STD_REL_GSRD_PR
U-Boot https://github.com/altera-opensource/u-boot-socfpga socfpga_v2024.07/QPDS24.1STD_REL_GSRD_PR
Linux kernel https://github.com/altera-opensource/linux-socfpga socfpga-6.6.51-lts/QPDS24.1STD_REL_GSRD_PR
GHRD https://github.com/altera-opensource/ghrd-socfpga master/QPDS24.1STD_REL_GSRD_PR
GSRD https://github.com/altera-opensource/gsrd-socfpga styhead/QPDS24.1STD_REL_GSRD_PR
Reference Designs Sources https://github.com/altera-opensource/meta-intel-fpga-refdes styhead/QPDS24.1STD_REL_GSRD_PR
Reference Design Recipes https://git.yoctoproject.org/git/meta-intel-fpga styhead/QPDS24.1STD_REL_GSRD_PR
Yocto Project https://git.openembedded.org/meta-openembedded styhead
Reference Yocto Project https://git.yoctoproject.org/git/poky.git/ styhead
ARM® Debugger https://www.intel.com/content/www/us/en/software-kit/846382/arm-development-studio-version-2024-1-for-intel-soc-fpga.html ARM DS 2024.1

Features Released

None

Fixed Issues

Issue Fixed Component Affected Scope
Device/Board
HSD
(Internal Use)
Remove override warning about redundant or duplicate configs in the socfpga_cyclone5_defconfig started on U-boot 2023.04. Commit IDs: 210adb0988 U-Boot Cyclone V 15015036930
Change CONFIG_HPS to CFG_HPS when generating the handoff using the Python script. The issue was seen in 2023.01. Commit IDs: b9afbc56f0 U-Boot Cyclone V 15015507511
Missing patch regarding Cyclone V for U-Boot 2024.07 that fixes the issue regarding booting on Cyclone V device. Commit IDs: c13fb267004c U-Boot Cyclone V 15017434439
Cyclone V GHRD build is failing, when not using the make all command. Commit IDs: e3bd58392f GHRD Cyclone V [15017126716
Unable to boot from SD Card using 23.1 STD. Failing at FSBL stage with the last message: Trying to boot from MMC1. Commit IDs: c13fb26700 U-Boot Cyclone V 16023469269

Known Issues

None

24.3.1 PRO Release

06 Feb 19:00

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Intel FPGA HPS Embedded Software Release Notes

Release Information

Version: Release 24.3.1 PRO
Tag: QPDS24.3.1_REL_GSRD_PR
Release Date: January 31st, 2025
Devices Affected: Agilex™ 5, Agilex™ 7
Release Type: Minor release/Binary release
Binary Release Path: https://releases.rocketboards.org/2025.01/

Note: Although new features supported in this release were focus on Agilex™ 5 and Agilex™ 7 devices, indirectly Stratix® 10 device was also affected after there is some shared code among them. Also, there were few fixed issues that affected the Stratix® 10, Cyclone® V and Arria® 10 devices.

Release Strategy

The HPS Embedded software releases for Intel FPGA devices are aligned with Quartus® releases and are scheduled as follows:

  • Quartus® Standard (STD): 1 release per year. This is a binary release.
  • Quartus® Pro (PRO): 4 releases per year, one each quarter. Some of these are Major release which affects most of the devices while Minor releases are released as needed and affect a few devices.

Embedded software releases can also be classified as Source code or Binary releases. A Source code release involves releasing only the source code in the software repositories. A Binary release consists of a source code release + pre-built binaries release that could be loaded directly into the development kits.

Note: To review the Release Notes prior 24.3.1 release please refer to the following link: https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease.

The source code and tools repositories with the current release branches or versions are shown next.

SW Component Release Repository Branch/Tag
Arm® Trusted Firmware https://github.com/altera-opensource/arm-trusted-firmware socfpga_v2.11.1/QPDS24.3.1_REL_GSRD_PR
U-Boot https://github.com/altera-opensource/u-boot-socfpga socfpga_v2024.07/QPDS24.3.1_REL_GSRD_PR
Linux kernel https://github.com/altera-opensource/linux-socfpga socfpga-6.6.51-lts/QPDS24.3.1_REL_GSRD_PR
GHRD https://github.com/altera-opensource/ghrd-socfpga master/QPDS24.3.1_REL_GSRD_PR
GSRD https://github.com/altera-opensource/gsrd-socfpga styhead/QPDS24.3.1_REL_GSRD_PR
Reference Designs Sources https://github.com/altera-opensource/meta-intel-fpga-refdes styhead/QPDS24.3.1_REL_GSRD_PR
Reference Design Recipes https://git.yoctoproject.org/git/meta-intel-fpga styhead/QPDS24.3.1_REL_GSRD_PR
Yocto Project https://git.openembedded.org/meta-openembedded styhead
Reference Yocto Project https://git.yoctoproject.org/git/poky.git/ styhead
Zephyr https://github.com/altera-opensource/zephyr-socfpga/ socfpga_rel_24.3/QPDS24.3_REL_GSRD_PR
Baremetal https://github.com/altera-fpga/baremetal-drivers main / 24.3
ARM® Debugger https://www.intel.com/content/www/us/en/software-kit/846382/arm-development-studio-version-2024-1-for-intel-soc-fpga.html ARM DS 2024.1

Features Released

Feature Description Component Affected Scope
Device/Board
HSD
(Internal Use)
Provide an example design(s) demonstrating simple TSN functionality including ptp4l, phc2sys, ethtool, tc, ip. GSRD Agilex™ 5 22014236672
Improved latency in SMC call in ATF by yeld immediately and just send a mailbox message. The Linux or non-secure software would poll the response. Commit IDs: d9182e80c1, 8bad787e85, ef74dadb1f, dfe710310d. ATF Agilex™5
Agilex™7
Stratix® 10
15011992914
Improved latency in SMC call in ATF by yeld immediately and just send a mailbox message. The Linux or non-secure software would poll the response. Commit IDs: 4edadb87549c14751cac7d17bd9a0df1f5863e00, c3f82a01e1, 22425012fd, 49a6eb948d, 9d1d3cca77, d8c0390957, eebb852778, 1605f0a44b. Linux Agilex™5
Agilex™7
Stratix® 10
15011993515
Hypervisor support. Added a separate modular add-on reference design that can builds seamlessly on top of the baseline of Agilex™ 5 E/D-Series GSRD, demonstrating Linux and Zephyr running side-by side in the HPS cluster. HPS has capability to boot hypervisor on main CPU core and launch Zephyr on secondary CPU core. Want to demonstrate separation of execution and memory. Commit IDs: f76229cbd8, 3835b20a77, 7e7d3a6c00. GSRD Agilex™ 5 18025905437
18027472935
Migrated GSRD for Agilex™ 7 FPGA F-Series SI Transceiver-SoC Development Kit from Enpirion (DK-SI-AGF014EA) to Linear version (DK-SI-AGF014EB). GSRD Agilex™ 7 18036345149
U-Boot: Provided ability to query the SDM configuration status and/or report errors seen by the SDM during FPGA configuration from HPS. Allowing U-Boot to query the SDM on configuration status and error log would help users find underlying cause of failure faster e.g., finding the SDM had logged messages such as missing ref clock for transceivers, or mis-matched FPGA core rbf (Phase 2) with HPS first image (Phase 1).The ask applies to all SDM-based SoC devices. Commit IDs: 0d9cd85d1d. U-Boot Agilex™ 5
Agilex™ 7
Stratix®10
18036484257
ATF: Provided ability to query the SDM configuration status and/or report errors seen by the SDM during FPGA configuration from HPS. Allowing U-Boot to query the SDM on configuration status and error log would help users find underlying cause of failure faster .e.g., finding the SDM had logged messages such as missing ref clock for transceivers, or mis-matched FPGA core rbf (Phase 2) with HPS first image (Phase 1).The ask applies to all SDM-based SoC devices. Commit IDs: da54890a35. ATF Agilex™ 5
Agilex™ 7
Stratix® 10
18036484257

Fixed Issues

Issue Fixed Component Affected Scope
Device/Board
HSD
(Internal Use)
Update GHRD for Agilex™ 5 Modular dev kit to use the official device MK- A5E065BB32AES1. Commit IDs: 4f170c94e5, f578fb674d, b60722a750. GHRD Agilex™ 5 15016519273
Cache is not flushed when a cold reset is triggered from U-Boot using reset command or through SMC call to ATF. Commit IDs: ccffa28b12. ATF Agilex™ 7 14022144130
Unable to boot up using ARM® DS using second boot core (A76). Workaround identified. ARM® DS Agilex™ 5 15016006295
15015204245
QIS and DA warnings are observed when ECC is enabled in Agilex™ 7 M-Series SOF. Commit IDs: f7fca206e9, 593900edff, 86312a166c GHRD Agilex™ 7 15016822102
Get the broad device ID from JTAG ID. The JTAG ID is read from the boot scratch cold 4 register, and based on the sub device type info retrieved from JTAG ID, the appropriate code path is executed to correct the erratum on the silicon. Commit IDs: aa9348797c U-Boot Agilex™ 5 15016529058
ATF FDT enhancement for future portability. Commit IDs: 69564808d9. ATF Agilex™ 5 15016396549
NAND failed to initialize on U-boot 2024.04 (Agilex™ 5 Power- Optimized). The test unable to initialize NAND controller. Commit IDs: 59be0e7 . GSRD Agilex™ 5 15016663458
Add DMAs fields to SPI Master nodes in Agilex™ 7 reference device tree. Commit IDs: 31dccee15c, 3b24c8869e. Linux Agilex™ 7 18039818253
Configure HPS Internal Oscillator as boot_clk source. Right now for non-secure boot, boot_clk is sourced from external oscillator (HPS_OSC_CLK) by default, it is required to Configure HPS Internal Oscillator as boot_clk source for non-secure boot. Commit IDs: 90fcd33585. U-Boot Agilex™ 5 15016500042
SSGDMA: Defining callback information to be shared between netdriver and ssgdma driver. Netdriver and SSGDMA driver need to share certain information which are needed for cleanup information and further processing. This information needs to be shared using the registered callback and its parameters. Linux Agilex™ 5 16025482961
Query on how the DEVICE_PORTS_IRQ_STATUS IRQ bits are interpreted by the SSGDMA software. As per the channel allocation the order of registration is in the order of MM, H2D ST, D2H ST. While the device IRQ status is read in the reverse order Linux Agilex™ 5 16025499228
SSGDMA: SSGDMA driver need to call netdriver registered callback even on terminate all. Netdriver registers callback along with a structure. These structures are important to it for cleanup on transfer completions. In case interface is shutdown net driver is going to call the terminate all of dmaengine, ssgdma driver should call the callback for all the descriptors, for a respective channel so that net driver can free the used resources. Linux Agilex™ 5 16025500389
SSGDMA:Current SSGDMA driver have only one descriptor block, user should have the flexibility to configure the no of descriptor block. If not given by user it should have a default descriptor block. Linux Agilex™ 5 16025510775
SSGDMA:D2H packets are not received after 1-2 initial startup packets. While the system is in loopback/Soc mode, HPS is sending packets, initial 1-2 packets are received, then reception stops. But we can observe from the Ethernet stat dump that the Ethernet HIP has sent and received the packets towards SSGDMA IP. Linux Agilex™ 5 16025872289
SSGDMA: In SSGDMA driver the spin lock obtained is not released on certain condition. Linux Agilex™ 5 16025997698
SSGDMA: watch dog error bit not cleared on error case. Linux Agilex™ 5 16025998365
SSGDMA: Interrupt handling in SSGDMA driver to be in sync with the interrupt mechanism in RTL. Linux Agilex™ 5 16026031481
SSGDMA: Understanding how circular data descriptor handled in corner case. Linux Agilex™ 5 16026078932
NAND driver probe fail when SMMU is enabled. If SMMU is enabled, SMMU initialize all the peripherals that is using iommu property first and then only it initializes...
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