feat(PeriphDrivers): Enhance I3C clock configuration for MAX32657#1496
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feat(PeriphDrivers): Enhance I3C clock configuration for MAX32657#1496
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Introduce enable and disable functions for both controller and target modes. This change allows clock settings to be modified after initialization. Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
I3C serial clock settings should now be applied outside the initialization sequence. Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Different I3C bus modes impose timing constraints that cannot be handled by the existing frequency-setting functions. Introduce new functions to individually configure the low and high periods for I3C push-pull, open-drain, and I2C clock modes. Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Mixed I3C bus mode requires the push-pull high period to be less than 45 ns. Additionally, a smaller high period enables finer-grained control of open-drain and I2C clocks. Update the frequency-setting function to determine the minimum possible PPBAUD value. Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Fixes the position of I3C reset bit in GCR reset register 0. Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
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This pull request is stale because it has been open for 30 days with no activity. Remove stale label, commit, or comment or this will be closed in 7 days. |
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This pull request is stale because it has been open for 30 days with no activity. Remove stale label, commit, or comment or this will be closed in 7 days. |
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Description
Implement flexible I3C SCL configuration.
These changes address timing constraints imposed by different I3C bus modes.
Changes
MXC_I3C_RevA_SetPPFrequency()to find minimum push-pull high period.Checklist Before Requesting Review