GitHub - apinise/FIR_ASIC: FIR filter implemented in Verilog for ASIC layout using Cadence. · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 49 Commits
chip		chip
constraints		constraints
glpower		glpower
glsim		glsim
glsta		glsta
layout		layout
refC		refC
rtl		rtl
sim		sim
sta		sta
syn		syn

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FIR filter implemented in Verilog for ASIC layout using Cadence.

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