FinFET Circuit Design and Characterization

This GitHub repository documents the 10-day workshop on FinFET Circuit Design and Characterization using ASAP7 PDK offered by VSD Corp. Pvt. Ltd. attended as part of cohort 27 Aug - 05 Sept, 2025 10 - 19 Sept, 2025.

Table of Contents

Module #	Topic(s) Covered
Mod. 1	Scaling Beyond CMOS: FinFET Devices and Innovations Path To Zetta Scale Computing Introduction To FinFETs FEOL Innovations BEOL Innovations
Mod. 2	Lab-to-Simulation: 7nm FinFET Inverter Performance Analysis NFET DC Characteristics Using 7nm PDKs First Inverter Characteristics Using 7nm FinFETs Module 2 Assignment - 7nm Inverter Characterization
Mod. 3	Design of a BandGap Reference Circuit Theory: Design of a BGR Circuit Module 3 Assignent - Bandgap Reference Design and Simulation using Xschem

NOTE: Theory part of the BGR circuit needs to be added

1 - Scaling Beyond CMOS: FinFET Devices and Innovations

1.1 - Path To Zetta Scale Computing

1.1.1 - CMOS Evolution And Next-Gen Candidates

As CMOS technology approaches sub-1 nm nodes, conventional Dennard scaling has essentially ended, and further device scaling must rely on innovations across multiple domains: Patterning, Channel Engineering, Gate Stack Innovation, Interconnect Scaling, Device Architecture, and Design-Technology & System-Technology Co-Optimization.

1.2 - Introduction To FinFETs

FinFETs became necessary because planar MOS devices could no longer suppress short-channel effects at sub-30 nm gate lengths. By using a multi-gate 3D structure, FinFETs improved electrostatics, variability, subthreshold swing, and drive current density, while enabling lower $(V_{DD})$ operation. This combination extended CMOS scaling for a decade until the industry shift toward GAA nanosheets.

1.2.1 - Why FinFets ?

1) Electrostatic Integrity and Short-Channel Effects (SCEs)

• In planar MOSFETs, as the gate length $(L_g)$ scaled below ~30 nm, the gate lost control over the channel potential because the depletion regions of the source and drain began to overlap.
• This resulted in severe drain-induced barrier lowering (DIBL), threshold voltage $(V_T)$ roll-off, and increased subthreshold slope (SS) (> 70–80 mV/dec, compared to the ideal 60 mV/dec).
• FinFETs, being double-gate or tri-gate structures, increase the gate-to-channel coupling by wrapping the gate around the fin, thereby suppressing SCEs and enabling continued $L_g$ scaling into the sub-20 nm regime.

2) Improved Subthreshold Swing and Leakage Control

• Planar MOSFETs suffer from poor subthreshold slope due to weak gate coupling.
• FinFETs achieve subthreshold swing closer to the Boltzmann limit (≈60 mV/dec at 300 K) because the gate controls the channel from multiple sides.
• This translates to significantly reduced off-state current $(I_{off})$.

3) Enhanced Drive Current and Effective Channel Width

• The fin geometry introduces a 3D channel with effective width:
  $W_{eff} = 2H_{fin} + W_{fin}$

where $H_{fin}$ is the fin height and $W_{fin}$ is the fin width.

• By increasing fin height or using multiple fins in parallel, designers can boost the on-state drive current $(I_{on})$ without increasing the footprint, providing scalability in both performance and density.

4) Reduced Variability

• Random dopant fluctuations (RDF) in planar devices created large $(V_T)$ variability because planar MOSFETs required heavy channel doping to control SCEs.
• FinFETs achieve electrostatic control primarily through geometry (fin thickness $(T_{fin})$, which allows for undoped or lightly doped channels, reducing RDF and improving device uniformity.

5) Lower Operating Voltage $(V_{DD})$ and Power Efficiency

• With improved electrostatic control, FinFETs maintain performance at reduced supply voltages, enabling dynamic power scaling $(P \propto C V^2 f)$.
• Leakage suppression also reduces static power, a major contributor in advanced nodes.

6) Scalability Beyond Planar CMOS

• FinFETs were manufacturable using existing CMOS process extensions (HKMG integration, strain engineering) while providing a scaling path from 22 nm → 7 nm → 5 nm nodes.
• They act as the evolutionary bridge toward Gate-All-Around (GAA) nanosheet/nanowire FETs, where the gate fully wraps around the channel for even stronger control.

1.3 FEOL Innovations

1.3.1 - CMOS Technology Inflection Points

	Dennard Scaling Era (~1 µm to 32 nm)
~1 µm (1980s) – 180 nm (1999)	Supply voltage scaling enabled higher integration (Dennard scaling)
130 nm (2000)	Introduction of Cu BEOL (copper interconnects).
90 nm (2003)	Uniaxial strained Si for mobility boost.
65 nm (2005)	eSiGe + low-k dielectrics.
45 nm (2007)	Transition to high-k / metal gate (HKMG) (first HK-first, MG-last).
32 nm (2009)	HKMG + raised source/drain, improving leakage and variability.
	Post-Dennard / New Device Architectures (22 nm onward)
22 nm (2012)	Shift to FinFETs (Tri-Gate transistors) for leakage control
14 nm (2014)/ 10 nm (2016)	Multiple patterning (SADP, SAQP, LELELE) to continue scaling
7 nm (2018)	EUV lithography adoption.
5 nm (2020)	SiGe FinFET PMOS with EUV for better performance.
3/2/1.4 nm (2023-2025)	Transition to Gate-All-Around (GAA) nanosheet/ nano-wire FETs.
Sub-1 nm (future)	Exploration of CFET (stacked devices), 2D materials (e.g., MoS₂), and higher-k dielectrics for ultimate scaling.

1.3.2 - Standard Cell Area Scaling

As process nodes continues to shrink, classical scaling vectors (like gate pitch) become increasingly challenging. Scaling boosters aid traditional scaling vectors through various modifications and enhancements to a process node. They may be part of the process technology flow itself or as part of the standard cell library as part of the design-technology co-optimization (DTCO). By combining scaling boosters with slightly less aggressive classical scaling vectors, a process node can achieve similar transistors density while keeping the process cost in check.

1.3.2.1 - Track Reduction (Fin Depopulation in the context of FinFETs)

• Is a technique for improving the density of the standard cell library by reducing the number of fins per FinFET transistor or the height of the active N or P region.
• By reducing the height of the active region, the number of tracks is reduced thereby reducing the height of the standard cell and ultimately increasing the transistor density of the chip.
• In the case of FinFET, fin depopulation results in energy reduction but also performance reduction.

1.3.2.2 - Single Diffusion Break (SDB)

• Cell boundaries were traditionally padded with an additional dummy gate right after the active diffusion regions, at fin ends, for better cell control. As node scaling continued, due to cell height reduction, the portion of the area that makes up the dummy gate grew.
• Single Dummy Gate (SDG) or Single Diffusion Break (SDB) is a process enhancement technique that eliminates the extra padding around the cell edge when packaging multiple cells, thereby reducing the effective transistor density at the block and macro level.

1.3.2.3 - Contact Over Active Gate (COAG)

• Typically, the area between the end of the nMOS and pMOS devices is used as the gate contact hit location.
• Self-aligned Contact Over Active Gate (COAG) is a process enhancement technique that eliminates the need to land the contact outside of the active gate, allowing the gate contact to land directly over the active gate, thereby reducing the amount of space the end-to-end (ETE) spacing between devices.

1.3.2.4 - Buried Power Rail (BPR)

• Power rails (VDD, VSS) are buried below the active device layer instead of occupying tracks in the standard cell.
• Traditionally, power rails run in the first metal layers (M0/M1). By moving them below the device layer, the routing tracks in BEOL are freed for signal routing.
• BPR helps to increase the routing resources in standard cells leading to higher logic density, and reduces the cell height enabling tighter standard-cell libraries.
  It also helps lower the local IR drop by providing a shorter path for VDD/VSS distribution to the devices.

1.3.3 - Parasitic Resistance And Capacitance

As CMOS technology continues to scale beyond the planar MOSFET era into FinFET, Gate-All-Around FETs (GAAFETs), and Complementary FETs (CFETs), device performance is increasingly impacted by parasitic resistance $(R_{EXT})$ and parasitic capacitance $(C_{par})$. These parasitics, once secondary, now play a first-order role in determining drive current, delay, and energy efficiency at advanced nodes.

1.3.3.1 Parasitic Resistance

Planar MOSFETs	FinFETs	GAAFET	CFET
Contact width $(W_C)$ is nearly equal to the Gate width $(W_G)$: $\frac{W_C}{W_G} \sim 1$ Ratio of external to channel resistance: $\frac{R_{EXT}}{R_{ch}} < 1$ Channel resistance dominates; external resistance is relatively minor.	Conduction occurs through vertical fins, with current spreading across sidewalls. Effective width ratio: $\frac{W_C}{W_G} \approx \frac{P}{(2H_f + D_f)} \sim \frac{1}{3}$ Ratio of resistances: $\frac{R_{EXT}}{R_{ch}} \sim 1$ External resistance becomes comparable to channel resistance.	In nanosheet/nanowire GAAFETs, the contact width per effective gate width decreases further: $\frac{W_C}{W_G} \sim \frac{1}{6}$ $\frac{R_{EXT}}{R_{ch}} \sim 3$ External resistance dominates device performance.	CFETs (stacked N- and P-FETs) inherit nanosheet-like geometries with: $\frac{R_{EXT}}{R_{ch}} \sim 3$ Parasitic resistance remains a major limiting factor.

$\mathbf{R_{EXT}}$ Components
$\mathbf{R_{FEOL}}$: Front-End-Of-Line resistance from the source/drain diffusion region up to the silicide or first contact. $R_{EPI}$: Epitaxial resistance in the raised source/drain epitaxy.
$\mathbf{R_C}$: Contact resistance between the silicide (or epitaxial region) and the contact metal. Dominant component at advanced nodes. Determined by: Schottky barrier height (SBH) Interface quality Doping at the contact interface.
$\mathbf{R_{MOL}}$: Middle-Of-Line resistance - inludes resistance of the local interconnect stack connecting the contact to higher-level metal. $R_{TS}$: Transistor Spacer resistance - resistance of the narrow constriction where current passes under the spacer, between the gate edge and the raised source/drain. $R_{CA-TS}$: contribution of the contact area to transistor spacer path. $R_{CA}$: Contact area resistance
$\mathbf{R_{BEOL}}$: Back-End-Of-Line resistance - resistance from the global interconnect stack (Cu/Co/Ru wires, vias, etc.) including $R_{CA-BEOL}$.

Measurements of the contribution by each component of the parasitic resistances show that:

• In NFET: Contact resistance, $R_C$ dominates (~63% initially) which could be improved to within 10%-40%.
• In PFET: More evenly distributed between $R_C$ and $R_{EPI}$.

Improvement strategies:

• Lower the Schottky Barrier Height (SBH)
• High source/drain doping near the contacts

1.3.3.2 Parasitic Capacitance

As nodes shrink, the effective capacitance (C_eff) becomes dominated by parasitics:

• C_of: Overlap/fringe capacitance
• C_pc-ca: Contact-to-channel capacitance
• Node evolution:
  • 22 nm: C_g ~ 56%, parasitics minor.
  • 7 nm: Parasitics dominate (~85%), C_g ~ 15%.

Spacer Engineering:

• Spacer materials strongly influence parasitic capacitance.
• Low-k spacers reduce parasitic capacitance (SiN > SiBCN > SiOCN > SiCO)
• Ultimately Air spacers

1.3.4 - Device Scaling

As scaling approaches sub-5 nm gate lengths, conventional transistors face fundamental limits.
Challenges for sub-5nm gate length scaling:

• Direct source-to-drain tunneling increases drastically at ultra-short channels:
  • Need for high effective mass
• Electrostatics degrade due to surface roughness and thickness variations:
  • Need for uniform atomically thin materials
• $C_D$ high relative to $C_{OX}$ --> higher Subthreshold Slope
  • Need for low in-plane dielectric constant

This forces us to look for new channel materials - where Transition Metal Dichalcogenides (TMDs) offer a promising pathway in the sub-5nm regime.

Layered TMD semiconductor materials such as MoS₂, WS₂, MoTe₂, and WSe₂ offer these properties of atomically uniform thickness, higher effective mass and a tunable bandgap

Scaling Benefits:

• Suppressed source-to-drain tunneling: Dual-gate MoS₂ MOSFETs show up to 100× reduction in tunneling leakage compared to Si, due to larger bandgap and higher m*.
• Ultra-short channel feasibility: MoS₂-based devices have demonstrated gate lengths down to 1 nm (using a carbon nanotube gate).
• Energy efficiency: Reduced leakage allows large energy savings in ultra-low-power electronics.
• Excellent electrostatics: Near-ideal subthreshold slope (~65 mV/dec) and high Ion/Ioff ratios (~10⁶) have been demonstrated.

Device Demonstrations:

1 nm MoS₂ transistor
All 2D MOSFET
TMDs on 3D surfaces

1.3.5 - 3D-Structures

CFET, or Complementary FET, is a future transistor architecture that stacks NMOS and PMOS transistors vertically on top of each other to increase transistor density and reduce chip area. The CFET architecture is an evolution of a Gate-All-Around architecture, where the NFET and PFET are stacked vertically rather than side by side.

Two CFET manufacturing integration schemes have been proposed – one that grows the PFET and NFET together in a monolithic manner and the other that grows them sequentially. The monolithic approach offers better performance and lower cost. However, extremely high aspect ratio (HAR) etching is needed for monolithic integration. The sequential approach allows more flexibility in NFET and PFET channel materials. However, a very accurate NFET-PFET alignment is needed using sequential integration.

Ref: Monolithic 3D CMOS Using Layered Semiconductors

Quoting directly from the above paper:
"In all CMOS logic circuits, a pair of NMOS & PMOS transistors shares the same gate that accepts an input signal, and NMOS & PMOS transistors always exist in pairs. Taking inverter as an example, NMOS & PMOS transistors can be folded on top of each other along the line of symmetry (M–N) so that each pair of these transistors shares a common gate [Figure (d)]. The source and drain contacts for NMOS and PMOS transistors cannot be always shared and hence should be electrically isolated from each other and connected using metal lines as required. The resulting unit cell for 3D CMOS has an NMOS and a PMOS stacked on top of each other sharing a common gate metal and the source and drain contacts for the two transistors are electrically isolated as shown in Figure (b). Additional layers of logic gates and memory can be stacked over this layer separated with a thick dielectric called the interlayer dielectric to further increase the integration density."

References on CFET:

1. https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap
2. https://newsroom.lamresearch.com/understanding-cfets-transistor-architecture

1.4 - BEOL Innovations

Back-End-Of-Line (BEOL) interconnects — responsible for signal routing and power delivery — have become a critical performance bottleneck. While transistor performance has continued to scale, interconnect resistance and capacitance scaling lags behind, leading to delay, energy, and reliability issues.
Innovations in BEOL are therefore essential to sustain system-level scaling.

1.4.1 - Extending Copper Interconnects

At reduced pitches (≤ 28 nm), Cu resistivity rises due to size effects, scattering, and barrier/liner overheads.

Barrier and via metal optimization through Selective barrier deposition reduces via resistance by up to 50%, allowing Cu interconnects to remain viable down to ~3 nm nodes before a transition to alternative metals is required.

1.4.2 - Transition to Non-Cu Metals

As Cu scaling saturates, alternative metals like Ru, Co, Mo, Rh, Ir are explored.

Advantages:

• Improved electromigration (EM) reliability.
• Lower resisitivities and low electron scattering at small interconnect dimensions.

1.4.3 - Back-Side Power Delivery Network (BS-PDN)

In traditional front-side PDN (FS-PDN), power and signals share BEOL layers, leading to IR drop and routing congestion.
In Back-side PDN (BS-PDN), power delivery vias are routed through the wafer backside

• Reduction in IR-drop and power integrity.
• As the power delivery layers are separated, this frees up routing resources on the front-side metal layers for signal routing leading to reduced congestion and improved parasitic RC delays and thus performance.
• Helps decrease standard cell area by allowing tighter standard cell scaling (from 6-track to 5-track libraries).

---

2 - Lab-to-Simulation: 7nm FinFET Inverter Performance Analysis

The way the MOS model and OSDI files were all packaged into the symbol files and the subckt wrapper definition resulted in the transistor parameters l=7e-9 and nfin=14 getting hardcoded for both pmos and nmos, even if each instance's values are modified in xschem. This required us to edit the generated netlist manually every time a schematic change was made in xschem.

Moreover, if there is only 1 instance each of nmos & pmos, since it doesn't cause any issues, we may overlook the effect of the hardcoding if there are more instances reulting in wrong sizes for the transistors.

The recommended way to include OSDI lib is provided in the ngspice manual: https://ngspice.sourceforge.io/docs/ngspice-html-manual/manual.xhtml#magicparlabel-21886

The asap7 directory in the repo contains the modified files to follow the above method to use the OSDI models.

• The asap7 folder needs to be placed in the directory where we are creating the schematics in xschem.
• When using this with xschem, make the below changes in xschemrc From terminal:

gedit ~/.xschem/xschemrc &

# Change line no. 111 to:
set netlist_dir $env(PWD)

# Change line no. 118 to:
set local_netlist_dir 0

• Add the asap7.spice file using .include SPICE directive
• Pre-load the OSDI models in netlist using pre_osdi command inside .control section

2.1 - NFET DC Characteristics Using 7nm PDKs

2.1.1 - Parameter Shmoo with alter

SPICE Deck: nfet_char.spice

** sch_path: /home/vsduser/Desktop/asap_7nm_Xschem/nfet_char.sch
**.subckt nfet_char
VGS G GND 0.8
VDS D GND 0.8
Xnfet1 D G GND GND asap_7nm_nfet l=7e-9 nfin=14
**** begin user architecture code
* ==========================================
* NFET DC Characterization
* ==========================================
.include ./asap7/asap7.spice

.control
pre_osdi ./asap7/bsimcmg.osdi
run

let VDS_Val     = 0
let VDS_Max     = 0.8
let VDS_incr_step = 0.1

let VGS_Val     = 0
let VGS_Max     = 0.8
let VGS_incr_step = 0.1

** TRANSFER CHARACTERISTICS
dowhile VDS_Val <= VDS_Max
    dc VGS 0 0.8 0.01
    alter VDS VDS_Val
    run
    let VDS_Val = VDS_Val + VDS_incr_step
end

** OUTPUT CHARACTERISTICS
dowhile VGS_Val <= VGS_Max
    dc VDS 0 0.8 0.01
    alter VGS VGS_Val
    run
    let VGS_Val = VGS_Val + VGS_incr_step
end

** ID vs VGS for different VDS
plot (-dc1.VDS#branch) (-dc2.VDS#branch) (-dc3.VDS#branch) (-dc4.VDS#branch) (-dc5.VDS#branch) (-dc6.VDS#branch) (-dc7.VDS#branch) (-dc8.VDS#branch) (-dc9.VDS#branch)

** ID vs VDS for different VGS
plot (-dc10.VDS#branch) (-dc11.VDS#branch) (-dc12.VDS#branch) (-dc13.VDS#branch) (-dc14.VDS#branch) (-dc15.VDS#branch) (-dc16.VDS#branch) (-dc17.VDS#branch) (-dc18.VDS#branch)
.endc

**** end user architecture code
**.ends
.GLOBAL GND
.end

ID vs. VDS
ID vs. VGS

2.1.2 - Nested DC Sweep

SPICE Deck: nfet_char2.spice

** sch_path: /home/vsduser/Desktop/asap_7nm_Xschem/nfet_char2.sch
**.subckt nfet_char2
VGS G GND 0.7
VDS D GND 0.7
Xnfet1 D G GND GND asap_7nm_nfet l=7e-9 nfin=56
**** begin user architecture code

* ==========================================
* NFET DC Characterization
* ==========================================
.include ./asap7/asap7.spice

.control
pre_osdi ./asap7/bsimcmg.osdi
run
* =================================================
* 1) TRANSFER CHARACTERISTICS (Id vs Vgs for each Vds)
* First sweep is the inner loop (Vgs), second is the outer loop (Vds)
dc VGS 0 0.8 0.01 VDS 0 0.8 0.1
plot -i(VDS) vs v(G)

* =================================================
* 2) OUTPUT CHARACTERISTICS (Id vs Vds for each Vgs)
* First sweep is the inner loop (Vds), second is the outer loop (Vgs)
dc VDS 0 0.8 0.01 VGS 0 0.8 0.1
plot -i(VDS) vs v(D)
.endc

**** end user architecture code
**.ends
.GLOBAL GND
.end

ID vs. VDS
ID vs. VGS

2.2 - First Inverter Characteristics Using 7nm FinFETs

2.2.1 - Xschem schematic and SPICE directives for evaluating performance metrics

Xschem schematic

SPICE Deck: inverter_vtc.spice
Note:
Char Loop hardcoded to only Nfin_P=14, Nfin_N=14

** sch_path: /home/vsduser/Desktop/asap_7nm_Xschem/inverter_vtc.sch
**.subckt inverter_vtc
Vin Vin GND pulse({PULSE_VLO} {PULSE_VHI} 20p 10p 10p 40p 500p 1)
VDD VDD GND {VDD_V}
Xpfet1 Vout Vin VDD VDD asap_7nm_pfet l=7e-9 nfin={nfin_pmos}
Xnfet1 Vout Vin GND GND asap_7nm_nfet l=7e-9 nfin={nfin_nmos}

**** begin user architecture code
.include ./asap7/asap7.spice

.param nfin_pmos = 14
.param nfin_nmos = 14
.param VDD_V    = 0.7
.csparam VDD_V  = 'VDD_V'
.csparam VLOW   = '0.2 * VDD_V'
.csparam VMID   = '0.5 * VDD_V'
.csparam VHIGH  = '0.8 * VDD_V'

** Unique voltage offset added = 43.8mV
**    Sigma{ASCII(arun)}/10 = (97+114+117+110)/10 = 43.8mV
.param Vuniq = 0.0438

.param PULSE_VLO = '0 + Vuniq'
.param PULSE_VHI = 'VDD_V + Vuniq'

.temp 27

.control
    pre_osdi ./asap7/bsimcmg.osdi
    let nfin_typ    = 14

    let nfin_min    = nfin_typ
    let nfin_max    = nfin_typ
    let nfin_p = nfin_typ
    let nfin_n = nfin_typ

    echo "Nfin_P,Nfin_N,VM,Id_max,Av_max,vil,vih,vol,voh,NML,NMH,Gm_max,t_rise,t_fall,t_slew,f_slew_Hz,f_slew_GHz,tpHL,tpLH,t_pd,f_pd_Hz,f_pd_GHz,Id_peak_transient,energy_per_cycle,avg_power"  > cmos_inverter.csv

    dowhile nfin_p <= nfin_max
        let nfin_n = nfin_min
        alterparam nfin_nmos = $&nfin_n
        alterparam nfin_pmos = $&nfin_p
        dowhile nfin_n <= nfin_max
            echo "--------------------"
            echo "Nfin_P=$&nfin_p, Nfin_N=$&nfin_n"
            echo "--------------------"

            ** First run DC
            reset
            dc Vin 0 0.7 1m
            run
            plot Vout Vin

            *******************
            * DC measurements
            *******************
            * Switching Threshold (VM)
            meas DC VM FIND V(Vin) WHEN V(Vout)=V(Vin)

            * Drain Current (Id)
            let Id = VDD#branch
            plot Id
            meas DC Id_max MIN Id

            * Gain (Av)
            let gain_Av = abs(deriv(Vout))
            plot gain_Av
            meas DC Av_max MAX gain_Av

            * Vil, Vih, Vol, Voh, Noise Margin
            let dVout_dVin = deriv(Vout)
            meas DC vil FIND V(Vin) WHEN dVout_dVin=-1 cross=1
            meas DC voh FIND V(Vout) WHEN dVout_dVin=-1 cross=1
            meas DC vih FIND V(Vin) WHEN dVout_dVin=-1 cross=2
            meas DC vol FIND V(Vout) WHEN dVout_dVin=-1 cross=2
            let NML = vil - vol
            let NMH = voh - vih
            print NML
            print NMH

            * Transconductance, Gm
            let Gm = real(deriv(Id, Vin))
            plot Gm
            meas DC Gm_max MAX Gm

            * Output Resistance, Rout
            let R_out= deriv(Vout, Id)
            plot R_out

            shell sh -c "printf '%d,%d,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g' $&nfin_p $&nfin_n $&VM $&Id_max $&Av_max $&vil $&vih $&vol $&voh $&NML $&NMH $&Gm_max >> cmos_inverter.csv"

            *************************
            * Transient measurements
            *************************
            tran 1e-12 100e-12
            plot Vin Vout

            * Rise time, Fall time
            meas TRAN t_rise TRIG v(Vout) VAL=VLOW RISE=1 TARG v(Vout) VAL=VHIGH RISE=1
            meas TRAN t_fall TRIG v(Vout) VAL=VHIGH FALL=1 TARG v(Vout) VAL=VLOW FALL=1
            let t_slew      = t_rise + t_fall
            let t_slew_ps   = t_slew * 1e12
            let f_slew_Hz   = 1/ t_slew
            let f_slew_GHz  = f_slew_Hz/ 1e9
            print t_slew
            print f_slew_Hz

            ** Alternately,
            *
            * meas TRAN t1 WHEN v(Vout)=VLOW RISE=1
            * meas TRAN t2 WHEN v(Vout)=VHIGH RISE=1
            * let t_rise=(t2-t1)
            * print t_rise
            *
            * meas TRAN t3 WHEN v(Vout)=VHIGH FALL=1
            * meas TRAN t4 WHEN v(Vout)=VLOW FALL=1
            * let t_fall=(t4-t3)
            * print t_fall
            *

            * Propagation Delay, Frequency (prop. delay based)
            meas TRAN tpHL TRIG v(Vin) VAL=VMID RISE=1 TARG v(Vout) VAL=VMID FALL=1
            meas TRAN tpLH TRIG v(Vin) VAL=VMID FALL=1 TARG v(Vout) VAL=VMID RISE=1
            let t_pd        = (tpHL + tpLH)/ 2
            let t_pd_ps     = t_pd * 1e12
            let f_pd_Hz     = 1/ (2 * t_pd)
            let f_pd_GHz    = f_pd_Hz/ 1e9
            print t_pd
            print f_pd_Hz

            * Id, Power
            let Id_transient = VDD#branch
            plot Id_transient
            meas TRAN Id_peak_transient MIN Id_transient
            * Integral t1 to t2:
            *   t1 = start of pulse waveform (=PULSE_TD)
            *   t2 = end   of pulse waveform (= t1 + [tr+pw+tf])
            let t1 = 20p
            let t2 = t1 + (10p+40p+10p)
            meas TRAN Integral_Id INTEG Id_transient from={t1} to={t2}
            let energy_per_cycle = abs(Integral_Id * VDD_V)
            let avg_power = (energy_per_cycle / 60e-12)
            print energy_per_cycle
            print avg_power

            shell sh -c "printf ',%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g' $&t_rise $&t_fall $&t_slew $&f_slew_Hz $&f_slew_GHz $&tpHL $&tpLH $&t_pd $&f_pd_Hz $&f_pd_GHz $&Id_peak_transient $&energy_per_cycle $&avg_power >> cmos_inverter.csv"
            echo "" >> cmos_inverter.csv

            let nfin_n = nfin_n + 1
            alterparam nfin_nmos = $&nfin_n
        end
        let nfin_p = nfin_p + 1
    end

.endc

**** end user architecture code
**.ends
.GLOBAL GND
.GLOBAL VDD
.end

2.2.2: Extracting Inverter Performance Metrics

Ngspice console output showing measurements

DC Analysis: VTC Curve (Vout vs. Vin)

** Switching Threshold (VM)
meas DC VM FIND V(Vin) WHEN V(Vout)=V(Vin)

DC Analysis: Vil, Vol, Vol, Voh, Noise Margin

** Vil, Vih, Vol, Voh, Noise Margin
let dVout_dVin = deriv(Vout)
meas DC vil FIND V(Vin) WHEN dVout_dVin=-1 cross=1
meas DC voh FIND V(Vout) WHEN dVout_dVin=-1 cross=1
meas DC vih FIND V(Vin) WHEN dVout_dVin=-1 cross=2
meas DC vol FIND V(Vout) WHEN dVout_dVin=-1 cross=2
let NML = vil - vol
let NMH = voh - vih

DC Analysis: Drain Current (Id)

** Drain Current (Id)
let Id = VDD#branch
plot Id
meas DC Id_max MIN Id

DC Analysis: Gain (Av)

** Gain (Av)
let gain_Av = abs(deriv(Vout))
plot gain_Av
meas DC Av_max MAX gain_Av

DC Analysis: Transconductance (Gm)

** Transconductance, Gm
let Gm = real(deriv(Id, Vin))
plot Gm
meas DC Gm_max MAX Gm

DC Analysis: Output Resistance (Rout)

*** Output Resistance, Rout
let R_out= deriv(Vout, Id)
plot R_out

TRANsient Analysis: Vin, Vout waveforms

TRANsient Analysis: Rise time, Fall time, Frequency (f_slew)

.param VDD_V    = 0.7
.csparam VDD_V  = 'VDD_V'
.csparam VLOW   = '0.2 * VDD_V'
.csparam VHIGH  = '0.8 * VDD_V'

** Rise time, Fall time, f_slew
meas TRAN t_rise TRIG v(Vout) VAL=VLOW RISE=1 TARG v(Vout) VAL=VHIGH RISE=1
meas TRAN t_fall TRIG v(Vout) VAL=VHIGH FALL=1 TARG v(Vout) VAL=VLOW FALL=1
let t_slew      = t_rise + t_fall
let f_slew_Hz   = 1/ t_slew

TRANsient Analysis: Propagation Delay, Frequency (f_pd)

.csparam VMID   = '0.5 * VDD_V'

** Propagation Delay, Frequency (f_pd)
meas TRAN tpHL TRIG v(Vin) VAL=VMID RISE=1 TARG v(Vout) VAL=VMID FALL=1
meas TRAN tpLH TRIG v(Vin) VAL=VMID FALL=1 TARG v(Vout) VAL=VMID RISE=1
let t_pd        = (tpHL + tpLH)/ 2
let f_pd_Hz     = 1/ (2 * t_pd)

TRANsient Analysis: Switching Energy, Avg. Power

** Trasient Drain current, Id
let Id_transient = VDD#branch
plot Id_transient
meas TRAN Id_peak_transient MIN Id_transient

** Total Energy, Avg. Power per cycle
* Integral t1 to t2:
*   t1 = start of pulse waveform (=PULSE_TD)
*   t2 = end   of pulse waveform (= t1 + [tr+pw+tf])
let t1 = 20p
let t2 = t1 + (10p+40p+10p)
meas TRAN Integral_Id INTEG Id_transient from={t1} to={t2}
let energy_per_cycle = abs(Integral_Id * VDD_V)
let avg_power = (energy_per_cycle / 60e-12)

2.3 - Module 2 Assignment - 7nm Inverter Characterization

7nm FINFET CMOS Inverter Characterization for different Wp, Wn (Lp = Ln = 7nm)

SPICE Deck: inverter_char.spice
Notes:
1) Char Loop for Nfin_P=7-21, Nfin_N=7-21
2) Also, plots are commented out in below shmoo due to the large set of points.
(VTC, Id, Delay etc. plots for Nfin_P/N=14 were already provided in the preceeding section)

** sch_path: /home/vsduser/Desktop/asap_7nm_Xschem/inverter_char.sch
**.subckt inverter_char
Vin Vin GND pulse({PULSE_VLO} {PULSE_VHI} 20p 10p 10p 40p 500p 1)
VDD VDD GND {VDD_V}
Xpfet1 Vout Vin VDD VDD asap_7nm_pfet l=7e-9 nfin={nfin_pmos}
Xnfet1 Vout Vin GND GND asap_7nm_nfet l=7e-9 nfin={nfin_nmos}

**** begin user architecture code
.include ./asap7/asap7.spice

.param nfin_pmos = 14
.param nfin_nmos = 14
.param VDD_V    = 0.7
.csparam VDD_V  = 'VDD_V'
.csparam VLOW   = '0.2 * VDD_V'
.csparam VMID   = '0.5 * VDD_V'
.csparam VHIGH  = '0.8 * VDD_V'

** Unique voltage offset added = 43.8mV
**    Sigma{ASCII(arun)}/10 = (97+114+117+110)/10 = 43.8mV
.param Vuniq = 0.0438

.param PULSE_VLO = '0 + Vuniq'
.param PULSE_VHI = 'VDD_V + Vuniq'

.temp 27

.control
    pre_osdi ./asap7/bsimcmg.osdi
    let nfin_typ    = 14
    let nfin_min    = nfin_typ - (nfin_typ/ 2)
    let nfin_max    = nfin_typ + (nfin_typ/ 2)

    echo "Nfin_P,Nfin_N,VM,Id_max,Av_max,vil,vih,vol,voh,NML,NMH,Gm_max,t_rise,t_fall,t_slew,f_slew_Hz,f_slew_GHz,tpHL,tpLH,t_pd,f_pd_Hz,f_pd_GHz,Id_peak_transient,energy_per_cycle,avg_power"  > cmos_inverter.csv

    let nfin_p = nfin_min

    dowhile nfin_p <= nfin_max
        let nfin_n = nfin_min
        alterparam nfin_pmos = $&nfin_p
        alterparam nfin_nmos = $&nfin_n
        dowhile nfin_n <= nfin_max
            echo "--------------------"
            echo "Nfin_P=$&nfin_p, Nfin_N=$&nfin_n"
            echo "--------------------"

            ** First run DC
            reset
            dc Vin 0 0.7 1m
            run
            *plot Vout Vin

            *******************
            * DC measurements
            *******************
            * Switching Threshold (VM)
            meas DC VM FIND V(Vin) WHEN V(Vout)=V(Vin)

            * Drain Current (Id)
            let Id = VDD#branch
            *plot Id
            meas DC Id_max MIN Id

            * Gain (Av)
            let gain_Av = abs(deriv(Vout))
            *plot gain_Av
            meas DC Av_max MAX gain_Av

            * Vil, Vih, Vol, Voh, Noise Margin
            let dVout_dVin = deriv(Vout)
            meas DC vil FIND V(Vin) WHEN dVout_dVin=-1 cross=1
            meas DC voh FIND V(Vout) WHEN dVout_dVin=-1 cross=1
            meas DC vih FIND V(Vin) WHEN dVout_dVin=-1 cross=2
            meas DC vol FIND V(Vout) WHEN dVout_dVin=-1 cross=2
            let NML = vil - vol
            let NMH = voh - vih
            print NML
            print NMH

            * Transconductance, Gm
            let Gm = real(deriv(Id, Vin))
            *plot Gm
            meas DC Gm_max MAX Gm

            * Output Resistance, Rout
            let R_out= deriv(Vout, Id)
            *plot R_out

            shell sh -c "printf '%d,%d,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g' $&nfin_p $&nfin_n $&VM $&Id_max $&Av_max $&vil $&vih $&vol $&voh $&NML $&NMH $&Gm_max >> cmos_inverter.csv"

            *************************
            * Transient measurements
            *************************
            tran 1e-12 100e-12
            *plot Vin Vout

            * Rise time, Fall time
            meas TRAN t_rise TRIG v(Vout) VAL=VLOW RISE=1 TARG v(Vout) VAL=VHIGH RISE=1
            meas TRAN t_fall TRIG v(Vout) VAL=VHIGH FALL=1 TARG v(Vout) VAL=VLOW FALL=1
            let t_slew      = t_rise + t_fall
            let t_slew_ps   = t_slew * 1e12
            let f_slew_Hz   = 1/ t_slew
            let f_slew_GHz  = f_slew_Hz/ 1e9
            print t_slew
            print f_slew_Hz

            ** Alternately,
            *
            * meas TRAN t1 WHEN v(Vout)=VLOW RISE=1
            * meas TRAN t2 WHEN v(Vout)=VHIGH RISE=1
            * let t_rise=(t2-t1)
            * print t_rise
            *
            * meas TRAN t3 WHEN v(Vout)=VHIGH FALL=1
            * meas TRAN t4 WHEN v(Vout)=VLOW FALL=1
            * let t_fall=(t4-t3)
            * print t_fall
            *

            * Propagation Delay, Frequency (prop. delay based)
            meas TRAN tpHL TRIG v(Vin) VAL=VMID RISE=1 TARG v(Vout) VAL=VMID FALL=1
            meas TRAN tpLH TRIG v(Vin) VAL=VMID FALL=1 TARG v(Vout) VAL=VMID RISE=1
            let t_pd        = (tpHL + tpLH)/ 2
            let t_pd_ps     = t_pd * 1e12
            let f_pd_Hz     = 1/ (2 * t_pd)
            let f_pd_GHz    = f_pd_Hz/ 1e9
            print t_pd
            print f_pd_Hz

            * Id, Power
            let Id_transient = VDD#branch
            *plot Id_transient
            meas TRAN Id_peak_transient MIN Id_transient
            * Integral t1 to t2:
            *   t1 = start of pulse waveform (=PULSE_TD)
            *   t2 = end   of pulse waveform (= t1 + [tr+pw+tf])
            let t1 = 20p
            let t2 = t1 + (10p+40p+10p)
            meas TRAN Integral_Id INTEG Id_transient from={t1} to={t2}
            let energy_per_cycle = abs(Integral_Id * VDD_V)
            let avg_power = (energy_per_cycle / 60e-12)
            print energy_per_cycle
            print avg_power

            shell sh -c "printf ',%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g,%.4g' $&t_rise $&t_fall $&t_slew $&f_slew_Hz $&f_slew_GHz $&tpHL $&tpLH $&t_pd $&f_pd_Hz $&f_pd_GHz $&Id_peak_transient $&energy_per_cycle $&avg_power >> cmos_inverter.csv"
            echo "" >> cmos_inverter.csv

            let nfin_n = nfin_n + 1
            alterparam nfin_nmos = $&nfin_n
        end
        let nfin_p = nfin_p + 1
    end

.endc

**** end user architecture code
**.ends
.GLOBAL GND
.GLOBAL VDD
.end

Characterization Results:

• Characterization Table PDF
• Click on the image below to view graphs from the characterization data.

Observation needing closer look: tPHL, tpLH going negative for certain skewed Wp/Wn ratios.
[Edit: 2025-10-05] Reasons for the observation:

1. Vuniq offset voltage added to the Pulse input waveform is the major reason one of the reasons for this.
2. VM shifts by such a large value for certain extreme W/L ratios that measuring tpHL/ tpLH with a fixed VMID=(VDD/2) as the crossing reference point can cause negative measurement values. The highly skewed/ asymmetric pull-up vs. pull-down drive strengths is the smoking gun behind this.
3. Stimulus Pulse Input waveform Rise/ Fall time used.
   [Addendum]: This would be an independent variable and the characterization has to be done for multiple values of rise/ fall since the input slew rate is dependent on the input node's driver as well as its fan-out (load). Nevertheless, the stimulus input waveform rise/ fall time plays a role in the observation.
4. Transient analysis time step, dt used.
   [Addendum]: This would not make the values go negative, but it does affect the measurement accuracy. Ensure that the rising/ falling edge has sufficient number of sample points for accurate interpolation when calculating the time instants of threshold crossing.
5. CL=0 no-load condition (unrealistic in practicality) resulting in sharp output rise/ fall.
   [Addendum]: This is expected, but I was expecting the MOS parasitic capacitances at the output node be sufficient enough to not cause such -ve values. The extracted parasitics from the layout would give a much better picture.

• Negative_tp.xlsx: Contains few experiments for one particular case of negative prop. delay where input slew and simulation timestep are varied to study the effects.

It so happens that the above scenario matched perfectly what was explained in the artcile from the following webpage:
"Negative Propatation Delay"

Source: https://www.paripath.com/blog/characterization-blog/negative-propagation-delay

So only two of my queries are remaining to be clarified:
(1): What is the standard procedure while writing a characterization test bench by which we decide the appropiate timestep required for a transient analysis ?
Do we do a dummy run first to estimate the ballpark range of the cell's output rise/ fall times and then set the timestep accordingly ?
Do commercial simulators use adaptive stepping by default ?

(2): When we have circuits/ cells with highly skewed Pull-up/ Pull-down network drive strengths, what reference voltage should we use as the threshold point for propagation delay measurements ?
Is it a good idea to use the measured switching threshold (VM) from DC sim ?

---

3 - Design of a BandGap Reference Circuit

3.1 - Theory: Design of a BGR Circuit

3.2 - Module 3 Assignent - Bandgap Reference Design and Simulation using Xschem

Circuit Diagram based on which the schematic is drawn:

Ref: 1. Bandgap-Reference-Circuit-with-SBCM-with-ASAP-7nm-PDK 2. VSD Open 2021 BGR

BGR Schematic in Xschem showing Runiq

SPICE Deck: bgr_dc.spice

** sch_path: /home/vsduser/Desktop/asap_7nm_Xschem/bgr_dc.sch
**.subckt bgr_dc
Xpfet1 net6 net1 VDD VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet2 net1 net1 VDD VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet3 VREF net1 VDD VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet4 net2 net1 VDD VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet5 net3 net1 net2 VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet6 net6 net3 net1 VDD asap_7nm_pfet l=7e-9 nfin=14
Xnfet1 net6 net6 net7 GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet2 net7 net7 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet3 net1 net6 R1.1 GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet4 net3 net3 net4 GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet5 net4 net4 net5 GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet6 R1.2 R1.2 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet7 R1.2 R1.2 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet8 R1.2 R1.2 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet9 R1.2 R1.2 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet10 VCTAT VCTAT GND GND asap_7nm_nfet l=7e-9 nfin=14
R1 R1.1 R1.2 33k m=1
R2 VREF VCTAT 50k m=1
VDD VDD GND 1
R3 net5 GND 438 m=1

**** begin user architecture code
.include ./asap7/asap7.spice

.dc temp -45 150 1

.control
pre_osdi ./asap7/bsimcmg.osdi
run

let VPTAT = V(R1.1)-V(R1.2)
let dVREF_dT = deriv(V(VREF)) * 1e6

plot VPTAT
plot V(VCTAT)
plot V(VREF)
plot dVREF_dT

meas DC VPTAT_Max MAX VPTAT
meas DC VPTAT_Min MIN VPTAT

meas DC VCTAT_Max MAX V(VCTAT)
meas DC VCTAT_Min MIN V(VCTAT)

meas DC VREF_Min MIN V(VREF)
meas DC VREF_Max MAX V(VREF)
meas DC T0 WHEN V(VREF)=VREF_Max

let VPTAT_Slope = (VPTAT_Max - VPTAT_Min)/ 195
let VCTAT_Slope = (VCTAT_Min - VCTAT_Max)/ 195
print VPTAT_Slope
print VCTAT_Slope
.endc

**** end user architecture code
**.ends
.GLOBAL VDD
.GLOBAL GND
.end

DC Analysis: Temperature Sweep Results

Ngspice Console Log

VCTAT	VPTAT
VREF	d(VREF)/dT

TRANsient Analysis (VDD = 1V, Temp = 27C)

SPICE Deck for TRANsient Analysis:

** sch_path: /home/vsduser/Desktop/asap_7nm_Xschem/bgr_tran.sch
**.subckt bgr_tran
Xpfet1 net6 net1 VDD VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet2 net1 net1 VDD VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet3 VREF net1 VDD VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet4 net2 net1 VDD VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet5 net3 net1 net2 VDD asap_7nm_pfet l=7e-9 nfin=14
Xpfet6 net6 net3 net1 VDD asap_7nm_pfet l=7e-9 nfin=14
Xnfet1 net6 net6 net7 GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet2 net7 net7 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet3 net1 net6 R1.1 GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet4 net3 net3 net4 GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet5 net4 net4 net5 GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet6 R1.2 R1.2 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet7 R1.2 R1.2 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet8 R1.2 R1.2 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet9 R1.2 R1.2 GND GND asap_7nm_nfet l=7e-9 nfin=14
Xnfet10 VCTAT VCTAT GND GND asap_7nm_nfet l=7e-9 nfin=14
R1 R1.1 R1.2 33k m=1
R2 VREF VCTAT 50k m=1
VDD VDD GND 1
R3 net5 GND 438 m=1

**** begin user architecture code
.include ./asap7/asap7.spice

.temp 27
**.ic V(VDD)=0 V(net1)=0 V(net3)=0 V(net6)=0
.tran 1p 20n uic

.control
pre_osdi ./asap7/bsimcmg.osdi
run

let VPTAT = V(R1.1) - V(R1.2)
plot VPTAT xlimit 0 80p
plot V(VCTAT) xlimit 0 80p
plot V(VREF) xlimit 0 80p

meas tran VREF_Final FIND V(VREF) AT=20n
let VREF_TOLERANCE = 1/100
let VREF_Final_TOL = (1 - VREF_TOLERANCE) * VREF_Final
meas tran startup_time WHEN V(VREF)=VREF_Final_TOL RISE=1
print startup_time
.endc

**** end user architecture code
**.ends
.GLOBAL VDD
.GLOBAL GND
.end

Ngspice Console Log

VREF
VPTAT	VCTAT

BGRef Characterization Table

Note:

• We haven't performed the actual proper design of the BandGap Vref circuit in ASAP7, in the sense that we haven't calculated the bias currents & bias voltages, transistor sizing, resistor values etc.

• The reference repo also does not contain any design details/ calculations in this regard

• Also, we haven't extracted the required nMOS & pMOS characteristics for the ASAP7 process to be used in the calculations (All we have from the nMOS char done in lab 1 are the nMOS VTH at around 0.18V and Drain current ranges in saturation for a 7nm long, 14 fin Finfet)

• So what we have done instead (as in the reference repo) is to replace all MOSFETs in the base circuit diagram by n/pMOS with [L=7nm, W=14 fins], and BJTs by diode connected NMOSes. It is still doubtful to me whether a diode-connected NMOS can be used as a replacement for a diode-connected BJT to function as a proper CTAT. Even if it could be used that way, we haven't done the necessary calculations to fix their operating point in saturation (I=V^2) or sub-threshold (I=e^V) Hence, we are left to figure out the operating points, range of resistor values and even the range of allowed VDD values by trial and error!

• So without all the above, the characterization data of the BG Reference in the below table is only for representation purposes and not of any practical value.

---

References:

• Kunal Ghosh (VSD Corp. Pvt. Ltd.)
• https://github.com/RSMadhuri66/Bandgap-Reference-Circuit-with-SCMB-with-ASAP-7nm-PDK-
• https://github.com/vsdip/vsdopen2021_bgr

---

Miscellaneous Notes:

1. Interestingly, Ngspice's SPICE engine does not seem to support .step param. Instead alter or alterparam inside a loop. See: Section 12.14.4.3 in Ngspice Manual
2. It looks like in Ngspice, we can only plot currents through (independent) voltage sources. It is possible to put i(Vx), but not i(Rx),. etc. To workaround this, we can add a 0V source (say, Vdummy) in whatever branch of the circuit we want to plot the current through and then: plot i(Vdummy)
3. Scaling Booster
4. ST AN2386 - Threshold voltage thermal coefficient of the MOSFET