This repository has been made in order to generate RTL from modified RISCV cores. The first one used is the RISC-MINI in which an ALU was added. The second one concerns BOOM core for which we generated a 4ALU core and a smallBoomConfig that has 1ALU.
This repository was archived by the owner on Nov 1, 2025. It is now read-only.
azimgivron/3DIntegrationWithChisel
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