Evelien

controller.vhdl

@@ -0,0 +1,138 @@
+library IEEE;
+-- Hier komen de gebruikte libraries:
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+entity controller is
+port ( clk : in std_logic;
+reset : in std_logic;
+
+sensor_l : in std_logic;
+sensor_m : in std_logic;
+sensor_r : in std_logic;
+mine_detect: in std_logic;
+count_in : in std_logic_vector (19 downto 0);
+count_reset : out std_logic;
+
+motor_l_reset : out std_logic;
+motor_l_direction : out std_logic;
+
+motor_r_reset : out std_logic;
+motor_r_direction : out std_logic
+);
+end entity controller;
+
+architecture controller_behav of controller is
+type diff_states is (Startturn,Sensor_check,Wait_for_line);
+signal state, next_state: diff_states;
+signal sensor: std_logic_vector(2 downto 0); 
+signal mine : std_logic; -- using for being in state mine_detect.
+signal motorreset: std_logic;
+signal reset_l_motor, reset_r_motor: std_logic;
+begin
+sensor(2)<=sensor_l;
+sensor(1)<=sensor_m;
+sensor(0)<=sensor_r;
+ttl:process(sensor,state,mine_detect)
+  begin
+case state is
+when Startturn =>
+motor_l_direction <= '1';
+motor_r_direction <= '1';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+if(sensor="111") then
+next_state <= Wait_for_line;
+else next_state<=Startturn;
+end if;
+when Wait_for_line =>
+motor_l_direction <= '1';
+motor_r_direction <= '1';
+if(sensor="110") then
+next_state <= Sensor_check;
+else next_state <= Wait_for_line;
+end if;
+when Sensor_check=>
+if (sensor="000") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "001") then
+        motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '1';
+reset_r_motor <= '0';
+
+elsif(sensor= "010") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "011") then
+        motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "100") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_r_motor <= '1';
+reset_l_motor <= '0';
+
+elsif(sensor= "101") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "110") then
+motor_l_direction <= '1';
+        motor_r_direction <= '1';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "111") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+else
+motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+        end if;
+if(mine_detect='1') then
+next_state<=Startturn;
+else
+next_state<=Sensor_check;
+end if;
+     end case;       
+end process;
+clk_sig: process(clk,reset)
+begin
+if (reset='1') then
+    count_reset <= '1';
+    motorreset <= '1';
+    state<=Sensor_check;
+    elsif (clk'event and clk='1') then
+state<=next_state;
+        if (unsigned(count_in) =1000000) then
+      count_reset <= '1';
+      motorreset <= '1';
+    else
+      count_reset <= '0';
+      motorreset <= '0';
+    end if;
+end if;
+end process;
+
+motor_l_reset <= reset_l_motor or motorreset;
+motor_r_reset <= reset_r_motor or motorreset;
+
+end controller_behav;

vhdl_source/Top.vhdl

@@ -46,8 +46,8 @@ architecture structural of top is
 			write_data	: out std_logic; 
 			read_data	: out std_logic;  
 			new_data	: in std_logic;
-			data_out	: in std_logic_vector(7 downto 0);
-			data_in		: out std_logic_vector(7 downto 0);
+			data_received	: in std_logic_vector(7 downto 0);
+			data_send	: out std_logic_vector(7 downto 0);
 
 			motor_l_pwm     : out   std_logic;
 			motor_r_pwm     : out   std_logic
@@ -75,8 +75,8 @@ L2: robot port map(	clk=>clk,
 			mine_sensor =>mine_sensor,
 			motor_r_pwm=>motor_r_pwm,
 			motor_l_pwm=>motor_l_pwm,
-			data_in=>data_in_sig,
-			data_out=>data_out_sig,
+			data_send=>data_in_sig,
+			data_received=>data_out_sig,
 			write_data=>write_data_sig,
 			read_data=>read_data_sig,
 			new_data=>new_data_sig

vhdl_source/controller.vhdl

@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 use IEEE.std_logic_1164.all;
 
 entity controller is
+
 	port ( clk : in std_logic;
 		reset : in std_logic;
 
@@ -31,7 +32,7 @@ entity controller is
 end entity controller;
 
 architecture controller_behav of controller is
-	type diff_states is (Startturn,Sensor_check,Wait_for_line,Mine_signal);
+	type diff_states is (Startturn,Sensor_check,Wait_for_line,Mine_revert,Mine_send);
 	signal state, next_state: diff_states;
 	signal sensor: std_logic_vector(2 downto 0); 
 	signal mine : std_logic; -- using for being in state mine_detect.
@@ -41,18 +42,18 @@ begin
 	sensor(2)<=sensor_l;
 	sensor(1)<=sensor_m;
 	sensor(0)<=sensor_r;
-	data_send <= "11111111";
-	read_data <= '1';
-	write_data <= '0';
 
-	ttl:process(sensor,state,mine_detect)
+	ttl:process(sensor,state,mine_detect, count_in)
   	begin
 			case state is
 				when Startturn =>
 					motor_l_direction <= '1';
 					motor_r_direction <= '1';
 					reset_l_motor <= '0';
 					reset_r_motor <= '0';
+					read_data <= '1';
+					write_data <= '0';
+					data_send <= "11111111";
 					if(sensor="111") then
 						next_state <= Wait_for_line;
 					else 
@@ -63,21 +64,37 @@ begin
 					motor_r_direction <= '1';
 					reset_l_motor <= '0';
 					reset_r_motor <= '0';
+					read_data <= '1';
+					write_data <= '0';
+					data_send <= "11111111";
 					if(sensor="110") then
-						next_state <= Mine_signal;
+						next_state <= Mine_revert;
 					else 
 						next_state <= Wait_for_line;
 					end if;
-				when Mine_signal =>
+				when Mine_revert =>
 					motor_l_direction <= '1';
 					motor_r_direction <= '1';
-					reset_l_motor <= '1';
-					reset_r_motor <= '1';
-					read_data <= '0';
-					data_send <= "01101101";
+					reset_l_motor <= '0';
+					reset_r_motor <= '0';
+					if (unsigned(count_in) = 0) then
+						next_state <= Mine_send;
+					else
+						next_state <= Mine_revert;
+    					end if;
+				when Mine_send =>
+					motor_l_direction <= '1';
+					motor_r_direction <= '1';
+					reset_l_motor <= '0';
+					reset_r_motor <= '0';
+      					read_data <= '0';
 					write_data <= '1';
+					data_send <= "01101101";
 					next_state <= Sensor_check;
 				when Sensor_check=>
+					read_data <= '1';
+					write_data <= '0';
+					data_send <= "11111111";
 					if (sensor="000") then
 						motor_l_direction <= '1';
         					motor_r_direction <= '0';
@@ -161,4 +178,5 @@ begin
 	motor_l_reset <= reset_l_motor or motorreset;
 	motor_r_reset <= reset_r_motor or motorreset;
 
+
 end controller_behav;

vhdl_source/robot.vhdl

@@ -14,8 +14,8 @@ entity robot is
 		write_data	: out std_logic; 
 		read_data	: out std_logic;  
 		new_data	: in std_logic;
-		data_out	: in std_logic_vector(7 downto 0);
-		data_in		: out std_logic_vector(7 downto 0);
+		data_received	: in std_logic_vector(7 downto 0);
+		data_send	: out std_logic_vector(7 downto 0);
 
 		motor_l_pwm     : out   std_logic;
 		motor_r_pwm     : out   std_logic
@@ -36,7 +36,7 @@ architecture structural of robot is
 			read_data		: out std_logic;  
 			new_data		: in std_logic;
 			data_received		: in std_logic_vector(7 downto 0);
-			data_send			: out std_logic_vector(7 downto 0);
+			data_send		: out std_logic_vector(7 downto 0);
 
 			count_in		: in	std_logic_vector (19 downto 0);
 			count_reset		: out	std_logic;
@@ -129,8 +129,8 @@ L4: controller port map (	clk=>clk,
 				motor_r_reset=>motor_r_resets,
 				motor_l_direction=>motor_l_directions,
 				motor_r_direction=>motor_r_directions,
-				data_received=>data_out,
-				data_send=>data_in,
+				data_received=>data_received,
+				data_send=>data_send,
 				write_data=>write_data,
 				read_data=>read_data,
 				new_data=>new_data			

vhdl_source/uart.vhdl

@@ -5,12 +5,60 @@ use ieee.numeric_std.all;
 entity uart is
 	port (
 		clk, reset: in std_logic;
-		rx: in std_logic; -- input bit stream
+--		rx: in std_logic; -- input bit stream
 		tx: out std_logic; -- output bit stream
 		data_in: in std_logic_vector(7 downto 0); -- byte to be sent
 		data_out: out std_logic_vector(7 downto 0); -- received byte
 		write_data: in std_logic; -- write to transmitter buffer 
 		read_data: in std_logic; -- read from receiver buffer 
 		new_data: out std_logic -- new data available
 	);
-end uart;
+end uart;
+
+architecture structural of uart is 
+component uart_rx is
+   port(
+      clk, reset: in std_logic;
+--      rx: in std_logic; -- icoming serial bit stream
+      s_tick: in std_logic; -- sampling tick from baud rate generator
+      rx_done_tick: out std_logic; -- data frame completion tick
+      dout: out std_logic_vector(7 downto 0) -- data byte
+   );
+end component;
+component uart_tx is
+   port(
+      clk, reset: in std_logic;
+      tx_start: in std_logic; -- if '1' transmission starts
+      s_tick: in std_logic; -- sampling tick from baud rate generator
+      din: in std_logic_vector(7 downto 0); -- incoming data byte
+      tx_done_tick: out std_logic; -- data frame completion tick 
+      tx: out std_logic -- outcoming bit stream
+   );
+end component;
+component buf_reg is
+   port(
+      clk, reset: in std_logic;
+      clr_flag, set_flag: in std_logic; 
+      din: in std_logic_vector(7 downto 0);
+      dout: out std_logic_vector(7 downto 0);
+      flag: out std_logic
+   );
+end component;
+component baud_gen is
+   generic(
+      M: integer := 326 -- baud rate divisor M = 50M/(16*9600)
+  );
+   port(
+      clk, reset: in std_logic;
+      s_tick: out std_logic -- sampling tick
+   );
+end component;
+signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
+signal dout_rx, din_tx : std_logic_vector(7 downto 0);
+begin
+--U1: uart_rx port map (clk => clk, reset=> reset, rx=>rx,s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
+U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
+U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
+U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
+U5: baud_gen port map (clk=>clk, reset => reset, s_tick =>s_tick_buf);
+end structural;