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armv8m: make the debugger handle better faults through ICSR #2187

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armv8m: make the debugger handle better faults through ICSR #2187

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18 changes: 17 additions & 1 deletion src/target/cortexm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -864,7 +864,23 @@ static target_halt_reason_e cortexm_halt_poll(target_s *target, target_addr64_t
priv->dcache_enabled = ccr & CORTEXM_CCR_DCACHE_ENABLE;
priv->icache_enabled = ccr & CORTEXM_CCR_ICACHE_ENABLE;

if ((dfsr & CORTEXM_DFSR_VCATCH) && cortexm_fault_unwind(target))
bool fault_state = false;
// the V8 may stop before actually executing the instruction
// so reading dfsr might not work.
// Instead, we check if there are pending faults on ICSR
// meaning we stopped while trying to execute a fault
// but maybe did not execut it
if ((target->target_options & CORTEXM_TOPT_FLAVOUR_V8M)) {
const uint32_t icsr = target_mem32_read32(target, CORTEXM_ICSR);
const uint32_t pending = CORTEXM_ICSR_VEC_PENDING(icsr);
if (pending != 0 && pending < 8) // catch all faults
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@dragonmux dragonmux Feb 3, 2026

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Given pending is unsigned, perhaps (pending > 0U && pending < 8U)? - also please let clang-format run here, the { should be on this line (or, well.. more the point.. aren't necessary with this if block at all).

Perhaps re-express this as fault_state = pending > 0U && pending < 8U;?

{
fault_state = true;
}
} else {
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@dragonmux dragonmux Feb 3, 2026

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Please drop the else block braces, they're not necessary and not part of the code base code style.

fault_state = !!(dfsr & CORTEXM_DFSR_VCATCH);
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@dragonmux dragonmux Feb 3, 2026

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Rather than using !! which is inobvious, please use != 0U on the end of the expression for the bool conversion - it won't change codegen, but it does improve code clarity by better expression your intent, which isn't to double negate the value, but rather to check the value is not 0.

}
if (fault_state && cortexm_fault_unwind(target))
return TARGET_HALT_FAULT;

/* Remember if we stopped on a breakpoint */
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7 changes: 7 additions & 0 deletions src/target/cortexm.h
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Expand Up @@ -69,6 +69,9 @@ extern unsigned cortexm_wait_timeout;
#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024U + (0x10U * (i)))
#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028U + (0x10U * (i)))

/* Arm V8 External Debug Fault Status Register */
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@dragonmux dragonmux Feb 3, 2026

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ARMv8

#define CORTEXM_EDFSR (CORTEXM_SCS_BASE + 0xf98U)
#define CORTEXM_ICSR (CORTEXM_SCS_BASE + 0xd04U)
/* Application Interrupt and Reset Control Register (AIRCR) */
#define CORTEXM_AIRCR_VECTKEY (0x05faU << 16U)
/* Bits 31:16 - Read as VECTKETSTAT, 0xfa05 */
Expand Down Expand Up @@ -188,6 +191,10 @@ extern unsigned cortexm_wait_timeout;
#define CORTEXM_XPSR_THUMB (1U << 24U)
#define CORTEXM_XPSR_EXCEPTION_MASK 0x0000001fU

/* ICSR for ArmV8m, the exception are the same as IPSR */
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@dragonmux dragonmux Feb 3, 2026

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ARMv8-M

#define CORTEXM_ICSR_VEC_PENDING(x) (((x) >> 12) & 0x1ff)
#define CORTEXM_ICSR_VEC_ACTIVE(x) (((x) >> 0) & 0x1ff)
Comment on lines +195 to +196
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@dragonmux dragonmux Feb 3, 2026

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Please suffix the numbers here with U so the bit shifting and masking is done unsigned.


bool cortexm_attach(target_s *target);
void cortexm_detach(target_s *target);
void cortexm_halt_resume(target_s *target, bool step);
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