[WIP]Support for sos filters and adding saturation logic to iir filter

filter_blocks/fda/filter_hw.py

@@ -48,17 +48,22 @@ def __init__(self, b=None, a=None):
         # A reference to the HDL block
         self.hardware = None
 
-    def set_coefficients(self, coeff_b, coeff_a=None):
+    def set_coefficients(self, coeff_b = None, coeff_a = None, sos = None):
         """Set filter coefficients.
 
         Args:
             coeff_b (list): list of numerator filter coefficients
             coeff_a (list): list of denominator filter coefficients
         """
-        self.b = tuple(coeff_b)
+        if coeff_b is not None:
+            self.b = tuple(coeff_b)
+
         if coeff_a is not None:
             self.a = tuple(coeff_a)
 
+        if sos is not None:
+            self.sos = sos
+
     def set_stimulus(self, sigin):
         """Set filter stimulus
 

filter_blocks/fda/fir.py

@@ -24,6 +24,7 @@ def __init__(self, b = None, a = None):
         self.direct_form_type = 1
         self.response = []
 
+
     def get_response(self):
         """Return filter output.
 
@@ -32,11 +33,26 @@ def get_response(self):
         """
         return self.response
 
+    def info(self):
+        """Print filter info"""
+        print("Filter type :", self.filter_type, "\n"
+              "Filter order :", len(self.b), "\n"
+              "Arithmatic :", "fixed", "\n"
+              "Coefficient format :", self.coef_word_format ,"\n"
+              "Input format :", self.input_word_format ,"\n"
+              "Accumulator size :", "\n"
+              "Output format :", self.output_word_format ,"\n"
+              "Round mode :", "no rounding", "\n"
+              "Overflow mode :" "no overflow"
+            )
+
     def run_sim(self):
         """Run filter simulation"""
+
         testfil = self.filter_block()
         testfil.run_sim()
 
+
     def convert(self, **kwargs):
         """Convert the HDL description to Verilog and VHDL.
         """
@@ -46,7 +62,7 @@ def convert(self, **kwargs):
         imax = 2**(w[0]-1)
 
         # small top-level wrapper
-        def filter_fir_top(hdl, clock, reset, x, xdv, y, ydv):
+        def filter_fir_top(hdl , clock, reset, x, xdv, y, ydv):
             sigin = Samples(x.min, x.max, self.input_word_format)
             sigin.data, sigin.data_valid = x, xdv
             sigout = Samples(y.min, y.max, self.output_word_format)
@@ -55,19 +71,21 @@ def filter_fir_top(hdl, clock, reset, x, xdv, y, ydv):
             rst = reset
             glbl = Global(clk, rst)
 
-            # choose appropriate filter
+            #choose appropriate filter
             fir_hdl = fir_df1.filter_fir
 
             fir = fir_hdl(glbl, sigin, sigout, self.b, self.coef_word_format,
                           shared_multiplier=self._shared_multiplier)
 
             fir.convert(**kwargs)
 
+
         clock = Clock(0, frequency=50e6)
         reset = Reset(1, active=0, async=True)
         x = Signal(intbv(0, min=-imax, max=imax))
         y = Signal(intbv(0, min=-omax, max=omax))
         xdv, ydv = Signal(bool(0)), Signal(bool(0))
+
 
         if self.hdl_target.lower() == 'verilog':
             filter_fir_top(hdl, clock, reset, x, xdv, y, ydv)
@@ -77,20 +95,22 @@ def filter_fir_top(hdl, clock, reset, x, xdv, y, ydv):
         else:
             raise ValueError('incorrect target HDL {}'.format(self.hdl_target))
 
+
+
     @hdl.block
     def filter_block(self):
-        """
-        This elaboration code will select the different structure and
-        implementations
-        """
+        """ this elaboration code will select the different structure and implementations"""
 
         w = self.input_word_format
         w_out = self.output_word_format
+        #print(self.input_word_format)
+        #print(self.coef_word_format)
         ymax = 2**(w[0]-1)
         vmax = 2**(2*w[0])
         omax = 2**(w_out[0]-1)
         xt = Samples(min=-ymax, max=ymax, word_format=self.input_word_format)
         yt = Samples(min=-omax, max=omax, word_format=self.output_word_format)
+        #yt = Samples(min=-vmax, max=vmax)
         xt.valid = bool(1)
         clock = Clock(0, frequency=50e6)
         reset = Reset(1, active=0, async=True)
@@ -100,34 +120,39 @@ def filter_block(self):
 
         # set numsample 
         numsample = len(self.sigin)
-        # process to record output in buffer
+        #process to record output in buffer
         rec_insts = yt.process_record(clock, num_samples=numsample)
 
+
         if self.filter_type == 'direct_form':
             if self.direct_form_type == 1:
                 # all filters will need the same interface ports, this should be do able
                 dfilter = fir_df1.filter_fir
-            else:
-                raise NotImplementedError
 
             if self.n_cascades > 0:
                 filter_insts = [None for _ in range(self.n_cascades)]
                 for ii in range(self.n_cascades):
                     pass
+ #                   filter_insts[ii] = fir_df1.filter_fir(
+ #                       glbl, sigin[ii], sigout[ii], b
+ #                   )
             else:
                 filter_insts = dfilter(glbl, xt, yt, self.b, self.coef_word_format)
 
+
+
+
         @hdl.instance
         def stimulus():
-            """record output in numpy array yt.sample_buffer"""
+            "record output in numpy array yt.sample_buffer"
             for k in self.sigin:
                 xt.data.next = int(k)
                 xt.valid = bool(1)
 
                 yt.record = True
                 yt.valid = True
                 yield clock.posedge
-                # Collect a sample from each filter
+                #Collect a sample from each filter
                 yt.record = False
                 yt.valid = False
 
@@ -139,44 +164,3 @@ def stimulus():
             raise StopSimulation()
 
         return hdl.instances()
-
-    @hdl.block
-    def process(self, glbl, smpi, smpo):
-        """FIR filter model.
-
-        Args:
-            glbl:
-            smpi: sample stream input
-            smpo: sample stream output
-
-        Not convertible
-        """
-        assert isinstance(smpi, Samples)
-        assert isinstance(smpo, Samples)
-
-        clock, reset = glbl.clock, glbl.reset
-        x, y = smpi, smpo
-        ntaps = len(self.b)
-        h = tuple(self.b)
-
-        xd = [0 for _ in range(len(h))]
-
-        @hdl.instance
-        def beh_proc():
-            while True:
-                yield clock.posedge
-
-                if x.valid:
-                    xd.insert(0, int(smpi.data))
-                    xd.pop(-1)
-
-                    sop = 0
-                    for ii in range(ntaps):
-                        sop = sop + (h[ii] * xd[ii])
-
-                    y.data.next = int(round(sop))
-                    y.valid.next = True
-                else:
-                    y.valid.next = False
-
-        return hdl.instances()

filter_blocks/fda/iir.py

@@ -4,12 +4,12 @@
 from myhdl import Signal, intbv, StopSimulation
 
 from .filter_hw import FilterHardware
-from ..iir import iir_df1
+from ..iir import iir_df1, iir_sos
 from filter_blocks.support import Clock, Reset, Global, Samples
 
 
 class FilterIIR(FilterHardware):
-    def __init__(self, b=None, a=None):
+    def __init__(self, b = None, a = None):
         """Contains IIR filter parameters. Parent Class : FilterHardware
             Args:
                 b (list of int): list of numerator coefficients.
@@ -37,9 +37,22 @@ def run_sim(self):
         """Run filter simulation"""
 
         testfil = self.filter_block()
-        # testfil.config_sim(trace=True)
+        #testfil.config_sim(trace=True)
         testfil.run_sim()
 
+    def info(self):
+        """Print filter info"""
+        print("Filter type :", self.filter_type, "\n"
+              "Filter order :", len(self.b), "\n"
+              "Arithmatic :", "fixed", "\n"
+              "Coefficient format :", self.coef_word_format ,"\n"
+              "Input format :", self.input_word_format ,"\n"
+              "Accumulator size :", "\n"
+              "Output format :", self.output_word_format ,"\n"
+              "Round mode :", "no rounding", "\n"
+              "Overflow mode :" "saturate"
+            )
+
     def convert(self, **kwargs):
         """Convert the HDL description to Verilog and VHDL.
         """
@@ -60,6 +73,7 @@ def filter_iir_top(hdl , clock, reset, x, xdv, y, ydv):
 
             # choose appropriate filter
             iir_hdl = iir_df1.filter_iir
+
             iir = iir_hdl(
                 glbl, sigin, sigout, self.b, self.a, self.coef_word_format,
                 shared_multiplier=self._shared_multiplier
@@ -71,6 +85,7 @@ def filter_iir_top(hdl , clock, reset, x, xdv, y, ydv):
         x = Signal(intbv(0, min=-imax, max=imax))
         y = Signal(intbv(0, min=-omax, max=omax))
         xdv, ydv = Signal(bool(0)), Signal(bool(0))
+
 
         if self.hdl_target.lower() == 'verilog':
             filter_iir_top(hdl, clock, reset, x, xdv, y, ydv)
@@ -87,7 +102,7 @@ def filter_block(self):
         w = self.input_word_format
         w_out = self.output_word_format
 
-        ymax = 2**(w[0]-1)
+        ymax = 2**(2*w[0]-1)
         vmax = 2**(2*w[0])
         omax = 2**(w_out[0]-1)
         xt = Samples(min=-ymax, max=ymax, word_format=self.input_word_format)
@@ -111,10 +126,11 @@ def filter_block(self):
 
             if self.n_cascades > 0:
                 # TODO: port the SOS iir into the latest set of interfaces
-                # filter_insts = iir_sos.filter_iir_sos(
-                #     glbl, xt, yt, self.b, self.a, self.coef_word_format
-                # )
+                #filter_insts = iir_sos.filter_iir_sos(
+                #     glbl, xt, yt, self.sos, self.coef_word_format
+                #)
                 pass
+
             else:
                 filter_insts = dfilter(
                     glbl, xt, yt, self.b, self.a, self.coef_word_format

filter_blocks/fir/fir_df1.py

@@ -6,6 +6,7 @@
 
 
 @hdl.block
+
 def filter_fir(glbl, sigin, sigout, b, coef_w, shared_multiplier=False):
     """Basic FIR direct-form I filter.