put checks behind an option

tmckay-sifive · tmckay-sifive · commit c1b5599fe3a1 · 2025-01-08T10:24:38.000-08:00
diff --git a/core/src/main/scala-2/chisel3/VerificationStatementMacros.scala b/core/src/main/scala-2/chisel3/VerificationStatementMacros.scala
@@ -44,16 +44,17 @@ object VerifStmtMacrosCompat {
     (p.source.file.name, p.line): @nowarn // suppress, there's no clear replacement
   }
 
-  private[chisel3] def resetToDisableMigrationChecks(label: String)(implicit sourceInfo: SourceInfo) = {
-    val disable = Module.disable.value
-    withDisable(Disable.Never) {
-      AssertProperty(
-        prop = ltl.Property.eventually(!disable),
-        label = Some(s"${label}_never_enabled")
-      )
-      CoverProperty(!disable, s"${label}_enabled")
+  private[chisel3] def resetToDisableMigrationChecks(label: String)(implicit sourceInfo: SourceInfo) =
+    if (Builder.emitVerifStatementDisableProperties) {
+      val disable = Module.disable.value
+      withDisable(Disable.Never) {
+        AssertProperty(
+          prop = ltl.Property.eventually(!disable),
+          label = Some(s"${label}_never_enabled")
+        )
+        CoverProperty(!disable, s"${label}_enabled")
+      }
     }
-  }
 
   object assert {
 
diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala b/core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
@@ -112,6 +112,7 @@ object Definition extends SourceInfoDoc {
         context.useLegacyWidth,
         context.includeUtilMetadata,
         context.useSRAMBlackbox,
+        context.emitVerifStatementDisableProperties,
         context.warningFilters,
         context.sourceRoots,
         Some(context.globalNamespace),
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -477,14 +477,15 @@ private[chisel3] class ChiselContext() {
 }
 
 private[chisel3] class DynamicContext(
-  val annotationSeq:       AnnotationSeq,
-  val throwOnFirstError:   Boolean,
-  val useLegacyWidth:      Boolean,
-  val includeUtilMetadata: Boolean,
-  val useSRAMBlackbox:     Boolean,
-  val warningFilters:      Seq[WarningFilter],
-  val sourceRoots:         Seq[File],
-  val defaultNamespace:    Option[Namespace],
+  val annotationSeq:                       AnnotationSeq,
+  val throwOnFirstError:                   Boolean,
+  val useLegacyWidth:                      Boolean,
+  val includeUtilMetadata:                 Boolean,
+  val useSRAMBlackbox:                     Boolean,
+  val emitVerifStatementDisableProperties: Boolean,
+  val warningFilters:                      Seq[WarningFilter],
+  val sourceRoots:                         Seq[File],
+  val defaultNamespace:                    Option[Namespace],
   // Definitions from other scopes in the same elaboration, use allDefinitions below
   val loggerOptions: LoggerOptions,
   val definitions:   ArrayBuffer[Definition[_]],
@@ -978,6 +979,9 @@ private[chisel3] object Builder extends LazyLogging {
 
   def useSRAMBlackbox: Boolean = dynamicContextVar.value.map(_.useSRAMBlackbox).getOrElse(false)
 
+  def emitVerifStatementDisableProperties: Boolean =
+    dynamicContextVar.value.map(_.emitVerifStatementDisableProperties).getOrElse(false)
+
   // Builds a RenameMap for all Views that do not correspond to a single Data
   // These Data give a fake ReferenceTarget for .toTarget and .toReferenceTarget that the returned
   // RenameMap can split into the constituent parts
diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -518,3 +518,17 @@ case object UseSRAMBlackbox extends NoTargetAnnotation with ChiselOption with Ha
     )
   )
 }
+
+case object EmitVerifStatementDisableProperties
+    extends NoTargetAnnotation
+    with ChiselOption
+    with HasShellOptions
+    with Unserializable {
+  val options = Seq(
+    new ShellOption[Unit](
+      longOption = "emit-verif-statement-disable-properties",
+      toAnnotationSeq = _ => Seq(EmitVerifStatementDisableProperties),
+      helpText = "Emit properties to check that Disable for verification statements is eventually toggled"
+    )
+  )
+}
diff --git a/src/main/scala/chisel3/stage/ChiselOptions.scala b/src/main/scala/chisel3/stage/ChiselOptions.scala
@@ -8,28 +8,30 @@ import chisel3.layer.Layer
 import java.io.File
 
 class ChiselOptions private[stage] (
-  val printFullStackTrace: Boolean = false,
-  val throwOnFirstError:   Boolean = false,
-  val outputFile:          Option[String] = None,
-  val chiselCircuit:       Option[Circuit] = None,
-  val sourceRoots:         Vector[File] = Vector.empty,
-  val warningFilters:      Vector[WarningFilter] = Vector.empty,
-  val useLegacyWidth:      Boolean = false,
-  val layerMap:            Map[Layer, Layer] = Map.empty,
-  val includeUtilMetadata: Boolean = false,
-  val useSRAMBlackbox:     Boolean = false) {
+  val printFullStackTrace:                 Boolean = false,
+  val throwOnFirstError:                   Boolean = false,
+  val outputFile:                          Option[String] = None,
+  val chiselCircuit:                       Option[Circuit] = None,
+  val sourceRoots:                         Vector[File] = Vector.empty,
+  val warningFilters:                      Vector[WarningFilter] = Vector.empty,
+  val useLegacyWidth:                      Boolean = false,
+  val layerMap:                            Map[Layer, Layer] = Map.empty,
+  val includeUtilMetadata:                 Boolean = false,
+  val useSRAMBlackbox:                     Boolean = false,
+  val emitVerifStatementDisableProperties: Boolean = false) {
 
   private[stage] def copy(
-    printFullStackTrace: Boolean = printFullStackTrace,
-    throwOnFirstError:   Boolean = throwOnFirstError,
-    outputFile:          Option[String] = outputFile,
-    chiselCircuit:       Option[Circuit] = chiselCircuit,
-    sourceRoots:         Vector[File] = sourceRoots,
-    warningFilters:      Vector[WarningFilter] = warningFilters,
-    useLegacyWidth:      Boolean = useLegacyWidth,
-    layerMap:            Map[Layer, Layer] = layerMap,
-    includeUtilMetadata: Boolean = includeUtilMetadata,
-    useSRAMBlackbox:     Boolean = useSRAMBlackbox
+    printFullStackTrace:                 Boolean = printFullStackTrace,
+    throwOnFirstError:                   Boolean = throwOnFirstError,
+    outputFile:                          Option[String] = outputFile,
+    chiselCircuit:                       Option[Circuit] = chiselCircuit,
+    sourceRoots:                         Vector[File] = sourceRoots,
+    warningFilters:                      Vector[WarningFilter] = warningFilters,
+    useLegacyWidth:                      Boolean = useLegacyWidth,
+    layerMap:                            Map[Layer, Layer] = layerMap,
+    includeUtilMetadata:                 Boolean = includeUtilMetadata,
+    useSRAMBlackbox:                     Boolean = useSRAMBlackbox,
+    emitVerifStatementDisableProperties: Boolean = emitVerifStatementDisableProperties
   ): ChiselOptions = {
 
     new ChiselOptions(
@@ -42,7 +44,8 @@ class ChiselOptions private[stage] (
       useLegacyWidth = useLegacyWidth,
       layerMap = layerMap,
       includeUtilMetadata = includeUtilMetadata,
-      useSRAMBlackbox = useSRAMBlackbox
+      useSRAMBlackbox = useSRAMBlackbox,
+      emitVerifStatementDisableProperties = emitVerifStatementDisableProperties
     )
 
   }
diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala
@@ -29,10 +29,11 @@ package object stage {
           case SourceRootAnnotation(s)       => c.copy(sourceRoots = c.sourceRoots :+ s)
           case a: WarningConfigurationAnnotation     => c.copy(warningFilters = c.warningFilters ++ a.filters)
           case a: WarningConfigurationFileAnnotation => c.copy(warningFilters = c.warningFilters ++ a.filters)
-          case UseLegacyWidthBehavior         => c.copy(useLegacyWidth = true)
-          case RemapLayer(oldLayer, newLayer) => c.copy(layerMap = c.layerMap + ((oldLayer, newLayer)))
-          case IncludeUtilMetadata            => c.copy(includeUtilMetadata = true)
-          case UseSRAMBlackbox                => c.copy(useSRAMBlackbox = true)
+          case UseLegacyWidthBehavior              => c.copy(useLegacyWidth = true)
+          case RemapLayer(oldLayer, newLayer)      => c.copy(layerMap = c.layerMap + ((oldLayer, newLayer)))
+          case IncludeUtilMetadata                 => c.copy(includeUtilMetadata = true)
+          case UseSRAMBlackbox                     => c.copy(useSRAMBlackbox = true)
+          case EmitVerifStatementDisableProperties => c.copy(emitVerifStatementDisableProperties = true)
         }
       }
 
diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala
@@ -45,6 +45,7 @@ class Elaborate extends Phase {
             chiselOptions.useLegacyWidth,
             chiselOptions.includeUtilMetadata,
             chiselOptions.useSRAMBlackbox,
+            chiselOptions.emitVerifStatementDisableProperties,
             chiselOptions.warningFilters,
             chiselOptions.sourceRoots,
             None,

Original file line number	Diff line number	Diff line change
`@@ -518,3 +518,17 @@ case object UseSRAMBlackbox extends NoTargetAnnotation with ChiselOption with Ha`
`518`	`518`	`)`
`519`	`519`	`)`
`520`	`520`	`}`
	`521`	`+`
	`522`	`+case object EmitVerifStatementDisableProperties`
	`523`	`+ extends NoTargetAnnotation`
	`524`	`+ with ChiselOption`
	`525`	`+ with HasShellOptions`
	`526`	`+ with Unserializable {`
	`527`	`+ val options = Seq(`
	`528`	`+ new ShellOption[Unit](`
	`529`	`+ longOption = "emit-verif-statement-disable-properties",`
	`530`	`+ toAnnotationSeq = _ => Seq(EmitVerifStatementDisableProperties),`
	`531`	`+ helpText = "Emit properties to check that Disable for verification statements is eventually toggled"`
	`532`	`+ )`
	`533`	`+ )`
	`534`	`+}`