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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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    Chisel: A Modern Hardware Design Language

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  6. firrtl firrtl Public archive

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Repositories

Showing 10 of 111 repositories
  • chips-alliance-website Public
    chipsalliance/chips-alliance-website’s past year of commit activity
    SCSS 4 MIT 6 8 8 Updated May 23, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 14 Apache-2.0 8 18 4 Updated May 23, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 112 Apache-2.0 59 141 63 Updated May 22, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 323 ISC 82 48 (5 issues need help) 24 Updated May 23, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 93 Apache-2.0 51 93 10 Updated May 22, 2025
  • t1 Public

    The highest performace Cray-like RISC-V Vector in the world.

    chipsalliance/t1’s past year of commit activity
    Scala 268 Apache-2.0 38 18 25 Updated May 22, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 19 Apache-2.0 18 54 6 Updated May 22, 2025
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 28 Apache-2.0 9 3 0 Updated May 22, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,272 Apache-2.0 627 332 (1 issue needs help) 149 Updated May 22, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 39 LGPL-3.0 675 0 0 Updated May 22, 2025
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