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This repository was archived by the owner on Jan 24, 2026. It is now read-only.

cpatulea/fpga_wsa1000u

 
 

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ThinkRF port of Ettus Research USRP1 FPGA code for the WSA1000U

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  • Verilog 88.7%
  • VHDL 8.6%
  • C 1.0%
  • Python 0.9%
  • Tcl 0.8%
  • Perl 0.0%