Skip to content

Fix right shift bit one bug #49

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Sep 10, 2024
Merged

Fix right shift bit one bug #49

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion chip8/cpu.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -699,7 +699,7 @@ def right_shift_reg(self):
self.v[0xF] = bit_one
self.last_op = f"SHR V{x:01X}"
else:
bit_one = self.v[x] & 0x1
bit_one = self.v[y] & 0x1
self.v[x] = self.v[y] >> 1
self.v[0xF] = bit_one
self.last_op = f"SHR V{x:01X}, V{y:01X}"
Expand Down
9 changes: 9 additions & 0 deletions test/test_chip8cpu.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -399,6 +399,15 @@ def test_right_shift_reg(self):
self.assertEqual(self.cpu.v[x], shifted_val)
self.assertEqual(self.cpu.v[0xF], bit_zero)

def test_right_shift_reg_y_bug(self):
self.cpu.shift_quirks = False
self.cpu.operand = 0x0120
self.cpu.v[1] = 0
self.cpu.v[2] = 1
self.cpu.right_shift_reg()
self.assertEqual(0, self.cpu.v[1])
self.assertEqual(1, self.cpu.v[0xF])

def test_subtract_reg_from_reg1(self):
for x in range(0xF):
for y in range(0xF):
Expand Down
Loading