Integrate lvds reader into existing lvds decoder #1
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| clock <= decoder_outclock; | ||
| clock <= clock_s; | ||
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| -- ALTLVDS and the sensor use different bit orderings |
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Is this the case? I've looked at my testbench code and the sample data appears to be shifted out LSB to MSB. In the simulation the parallel values were what I was expecting
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I thought the ALTLVDS documentation said it did MSB to LSB, but maybe I misread it. I was pretty tired when I wrote that part.
| to_fifo <= (others => '0'); | ||
| end if; | ||
| end if; | ||
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From what I understand this code simply instantiates lvds_reader_top and converts the output from an array into a 1D std_logic_vector as well as handling a little bit of alignment checking. Is this correct?
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Yeah. It flattens the output so it can easily be passed through a FIFO buffer. Not the best but it works
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| -- Basically a constant to check that all pll_locked signals are HIGH because Quartus | ||
| -- can't handle unary AND operations :( | ||
| constant check_pll_locked : std_logic_vector (NUM_CHANNELS downto 0) := (others => '1'); |
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After I changed the compiler to VHDL 2008 unary AND operations might actually work. I would need to test this though
| gen_lvds_ip : for i_gen in NUM_CHANNELS-1 downto 0 generate | ||
| inst_lvds_ip : lvds_reader_ip port map ( | ||
| pll_areset => lvds_pll_reset, | ||
| rx_channel_data_align(0) => lvds_bitslip(i_gen), | ||
| rx_in(0) => lvds_data_in(i_gen), | ||
| rx_inclock => lvds_clock_in, | ||
| rx_cda_max(0) => lvds_cda_max(i_gen), | ||
| rx_locked => pll_locked_extended(i_gen), | ||
| rx_out => lvds_data_array(i_gen), | ||
| rx_outclock => i_lvds_parallel_clock(i_gen) | ||
| ); |
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Nice. This looks a lot cleaner now.
| channel_select <= 0; | ||
| alignment_word <= (others => '0'); | ||
| current_data <= (others => '0'); | ||
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