Merge pull request #1267 from diffblue/port_with_value4

Verilog: KNOWNBUG test for unconnected input port with default value

Author: tautschnig

regression/verilog/modules/port_with_value4.desc

@@ -0,0 +1,15 @@
+KNOWNBUG
+port_with_value1.sv
+
+^\[main\.m1\.eq_a] always M\.a == 4: PROVED .*$
+^\[main\.m1\.eq_b] always M\.b == 5: PROVED .*$
+^\[main\.m1\.eq_c] always M\.c == 6: PROVED .*$
+^\[main\.m2\.eq_a] always M\.a == 4: PROVED .*$
+^\[main\.m2\.eq_b] always M\.b == 5: REFUTED$
+^\[main\.m2\.eq_c] always M\.c == 6: PROVED .*$
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This fails an assertion.

regression/verilog/modules/port_with_value4.sv

@@ -0,0 +1,16 @@
+module M(input [31:0] a = 1, b = 2, c = 3);
+
+  eq_a: assert final (a == 4);
+  eq_b: assert final (b == 5);
+  eq_c: assert final (c == 6);
+
+endmodule
+
+module main;
+  // should pass
+  M m1(4, 5, 6);
+
+  // should fail -- b will be 2
+  M m2(4, , 6);
+  
+endmodule