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Merge pull request #1273 from diffblue/input_and_output Build and Test HW-CBMC #4614: Commit 18f0827 pushed by tautschnig
9m 27s main
main
9m 27s
Merge pull request #1274 from diffblue/assignment-with-function-call1… Build and Test HW-CBMC #4613: Commit 9be7670 pushed by tautschnig
8m 45s main
main
8m 45s
Merge pull request #1272 from diffblue/nettype1-fix Build and Test HW-CBMC #4612: Commit dc46b78 pushed by tautschnig
7m 45s main
main
7m 45s
Verilog: prevent redeclaration of module ports Build and Test HW-CBMC #4611: Pull request #1273 synchronize by kroening
8m 47s input_and_output
input_and_output
8m 47s
Verilog: prevent redeclaration of module ports Syntactic checks #2998: Pull request #1273 synchronize by kroening
2m 49s input_and_output
input_and_output
2m 49s
Verilog: fix assignment-with-function-call1.sv test Build and Test HW-CBMC #4610: Pull request #1274 opened by kroening
18m 36s assignment-with-function-call1-fix
assignment-with-function-call1-fix
18m 36s
Verilog: fix assignment-with-function-call1.sv test Syntactic checks #2997: Pull request #1274 opened by kroening
3m 17s assignment-with-function-call1-fix
assignment-with-function-call1-fix
3m 17s
Verilog: prevent redeclaration of module ports Build and Test HW-CBMC #4609: Pull request #1273 opened by kroening
7m 44s input_and_output
input_and_output
7m 44s
Verilog: prevent redeclaration of module ports Syntactic checks #2996: Pull request #1273 opened by kroening
2m 22s input_and_output
input_and_output
2m 22s
SystemVerilog: net type declarations Build and Test HW-CBMC #4608: Pull request #1272 opened by kroening
9m 19s nettype1-fix
nettype1-fix
9m 19s
SystemVerilog: net type declarations Syntactic checks #2995: Pull request #1272 opened by kroening
1m 38s nettype1-fix
nettype1-fix
1m 38s
Verilog: ref port type Syntactic checks #2994: Pull request #1271 opened by kroening
2m 43s ref1
ref1
2m 43s
Verilog: ref port type Build and Test HW-CBMC #4607: Pull request #1271 opened by kroening
12m 20s ref1
ref1
12m 20s
Merge pull request #1269 from diffblue/operators1-splitup Build and Test HW-CBMC #4606: Commit 35a4586 pushed by tautschnig
9m 40s main
main
9m 40s
Verilog: split up test regression/verilog/operators1/main.v Syntactic checks #2993: Pull request #1269 synchronize by tautschnig
1m 42s operators1-splitup
operators1-splitup
1m 42s
Verilog: split up test regression/verilog/operators1/main.v Build and Test HW-CBMC #4605: Pull request #1269 synchronize by tautschnig
10m 10s operators1-splitup
operators1-splitup
10m 10s
Merge pull request #1270 from diffblue/bump-spot-2-14-2 Build and Test HW-CBMC #4604: Commit de19257 pushed by tautschnig
13m 50s main
main
13m 50s
solver-based neural ranking engine Build and Test HW-CBMC #4603: Pull request #524 synchronize by kroening
10m 4s solver-nuterm
solver-nuterm
10m 4s
solver-based neural ranking engine Syntactic checks #2992: Pull request #524 synchronize by kroening
2m 46s solver-nuterm
solver-nuterm
2m 46s
CI: bump spot to 2.14.2 Build and Test HW-CBMC #4602: Pull request #1270 opened by kroening
11m 6s bump-spot-2-14-2
bump-spot-2-14-2
11m 6s
CI: bump spot to 2.14.2 Syntactic checks #2991: Pull request #1270 opened by kroening
1m 40s bump-spot-2-14-2
bump-spot-2-14-2
1m 40s
Verilog: split up test regression/verilog/operators1/main.v Syntactic checks #2990: Pull request #1269 synchronize by kroening
1m 42s operators1-splitup
operators1-splitup
1m 42s
Verilog: split up test regression/verilog/operators1/main.v Build and Test HW-CBMC #4601: Pull request #1269 synchronize by kroening
11m 38s operators1-splitup
operators1-splitup
11m 38s
Verilog: split up test regression/verilog/operators1/main.v Syntactic checks #2989: Pull request #1269 opened by kroening
1m 32s operators1-splitup
operators1-splitup
1m 32s
Verilog: split up test regression/verilog/operators1/main.v Build and Test HW-CBMC #4600: Pull request #1269 opened by kroening
12m 32s operators1-splitup
operators1-splitup
12m 32s