Merge pull request #1480 from diffblue/verilog-bitwise-tests

Tests for Verilog bitwise operators

Author: tautschnig

regression/verilog/expressions/bitwise_and1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+bitwise_and1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This gives wrong answers.

regression/verilog/expressions/bitwise_and1.sv

@@ -0,0 +1,8 @@
+module main;
+
+  initial assert ((4'b0000 & 4'b01zx) === 4'b0000);
+  initial assert ((4'b1111 & 4'b01zx) === 4'b01xx);
+  initial assert ((4'bxxxx & 4'b01zx) === 4'b0xxx);
+  initial assert ((4'bzzzz & 4'b01zx) === 4'b0xxx);
+
+endmodule

regression/verilog/expressions/bitwise_or1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+bitwise_or1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This gives wrong answers.

regression/verilog/expressions/bitwise_or1.sv

@@ -0,0 +1,8 @@
+module main;
+
+  initial assert ((4'b0000 | 4'b01zx) === 4'b01xx);
+  initial assert ((4'b1111 | 4'b01zx) === 4'b1111);
+  initial assert ((4'bxxxx | 4'b01zx) === 4'bx1xx);
+  initial assert ((4'bzzzz | 4'b01zx) === 4'bx1xx);
+
+endmodule

regression/verilog/expressions/bitwise_xor1.desc

@@ -0,0 +1,7 @@
+CORE
+bitwise_xor1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/expressions/bitwise_xor1.sv

@@ -0,0 +1,8 @@
+module main;
+
+  initial assert ((4'b0000 ^ 4'b01zx) === 4'b01xx);
+  initial assert ((4'b1111 ^ 4'b01zx) === 4'b10xx);
+  initial assert ((4'bxxxx ^ 4'b01zx) === 4'bxxxx);
+  initial assert ((4'bzzzz ^ 4'b01zx) === 4'bxxxx);
+
+endmodule