Merge pull request #1274 from diffblue/assignment-with-function-call1-fix

Verilog: fix assignment-with-function-call1.sv test

Author: tautschnig

regression/verilog/assignments/assignment-with-function-call1.desc

@@ -1,10 +1,10 @@
-KNOWNBUG
+CORE
 assignment-with-function-call1.sv
---bound 1
+--bound 0
+^\[top\.assert\.1\] .* PROVED .*$
+^\[top\.assert\.2\] .* PROVED .*$
+^\[top\.assert\.3\] .* PROVED .*$
 ^EXIT=0$
 ^SIGNAL=0$
-^\[main.property.property1\] .* SUCCESS$
-^\[main.property.property2\] .* SUCCESS$
-^\[main.property.property3\] .* SUCCESS$
 --
 ^warning: ignoring

regression/verilog/assignments/assignment-with-function-call1.sv

@@ -11,7 +11,7 @@ module top(input [7:0] a, input [7:0] b);
              sum_1_2 = fn(1, 2),
              sum_2_3 = fn(2, 3);
 
-  assert property (sum_a_b==a+b);
+  assert property (sum_a_b==a[2:0]+b[2:0]);
 
   assert property (sum_1_2==3);