Verilog: KNOWNBUG test for type parameter

Author: kroening

regression/verilog/modules/type_parameters2.desc

@@ -0,0 +1,7 @@
+CORE
+type_parameters2.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/modules/type_parameters2.sv

@@ -0,0 +1,9 @@
+module main;
+
+  parameter type T1 = bit [31:0];
+
+  T1 some_data;
+
+  initial assert ($bits(some_data) == 32);
+
+endmodule