SystemVerilog: type parameter ports

Author: kroening

regression/verilog/modules/parameter_ports4.desc renamed to regression/verilog/modules/type_parameter_port1.desc

@@ -1,5 +1,5 @@
 KNOWNBUG
-parameter_ports4.sv
+type_parameter_port1.sv
 
 ^EXIT=0$
 ^SIGNAL=0$

regression/verilog/modules/parameter_ports4.sv renamed to regression/verilog/modules/type_parameter_port1.sv

@@ -1985,6 +1985,8 @@ list_of_variable_identifiers:
 parameter_port_declaration:
           TOK_PARAMETER data_type_or_implicit param_assignment
 		{ $$ = $3; }
+        | TOK_PARAMETER TOK_TYPE type_assignment
+		{ $$ = $3; }
 	| TOK_LOCALPARAM data_type_or_implicit param_assignment
 		{ $$ = $3; }
 	| data_type param_assignment
@@ -3161,7 +3163,10 @@ named_parameter_assignment_brace:
 	;
 
 ordered_parameter_assignment:
-          expression;
+          expression
+        | data_type
+		{ init($$, ID_type); stack_expr($$).type() = stack_type($1); }
+        ;
 
 named_parameter_assignment:
 	  '.' parameter_identifier '(' expression_opt ')'