@@ -149,9 +149,9 @@ class convert_trans_to_netlistt:public messaget
149149
150150 std::optional<exprt> convert_property (const exprt &);
151151
152- void map_vars (
153- const irep_idt & module ,
154- netlistt &dest );
152+ var_mapt build_var_map ( const irep_idt & module );
153+
154+ void allocate_state_variables ( netlistt &);
155155};
156156
157157/* ******************************************************************\
@@ -190,7 +190,7 @@ literalt convert_trans_to_netlistt::new_input()
190190
191191/* ******************************************************************\
192192
193- Function: convert_trans_to_netlistt::map_vars
193+ Function: convert_trans_to_netlistt::build_var_map
194194
195195 Inputs:
196196
@@ -200,13 +200,13 @@ Function: convert_trans_to_netlistt::map_vars
200200
201201\*******************************************************************/
202202
203- void convert_trans_to_netlistt::map_vars (
204- const irep_idt &module ,
205- netlistt &dest)
203+ var_mapt convert_trans_to_netlistt::build_var_map (const irep_idt &module )
206204{
207205 boolbv_widtht boolbv_width (ns);
206+ var_mapt var_map;
208207
209- auto update_dest_var_map = [&dest, &boolbv_width](const symbolt &symbol) {
208+ auto update_dest_var_map = [&var_map, &boolbv_width](const symbolt &symbol)
209+ {
210210 var_mapt::vart::vartypet vartype;
211211
212212 if (symbol.is_property )
@@ -248,39 +248,51 @@ void convert_trans_to_netlistt::map_vars(
248248 if (size == 0 )
249249 return ;
250250
251- var_mapt::vart &var = dest. var_map .map [symbol.name ];
251+ var_mapt::vart &var = var_map.map [symbol.name ];
252252 var.vartype = vartype;
253253 var.type = symbol.type ;
254254 var.mode = symbol.mode ;
255255 var.bits .resize (size);
256-
257- for (std::size_t bit = 0 ; bit < size; bit++) {
258- // just initialize with something
259- var.bits [bit].current = const_literal (false );
260- var.bits [bit].next = const_literal (false );
261-
262- // we already know the numbers of inputs and latches
263- if (var.is_input () || var.is_latch ())
264- var.bits [bit].current = dest.new_var_node ();
265- }
266256 };
267257
268- // get the symbols in the given module
269- std::vector<const symbolt *> module_symbols;
270-
271258 for (const auto &symbol_it : symbol_table.symbols )
272259 if (symbol_it.second .module == module )
273- module_symbols.push_back (&symbol_it.second );
260+ update_dest_var_map (symbol_it.second );
261+
262+ return var_map;
263+ }
264+
265+ /* ******************************************************************\
266+
267+ Function: convert_trans_to_netlistt::allocate_state_variables
268+
269+ Inputs:
270+
271+ Outputs:
274272
275- // we sort them to get a stable netlist
276- std::sort (
277- module_symbols.begin (),
278- module_symbols.end (),
279- [](const symbolt *a, const symbolt *b)
280- { return a->name .compare (b->name ) < 0 ; });
273+ Purpose:
281274
282- for (auto symbol_ptr : module_symbols)
283- update_dest_var_map (*symbol_ptr);
275+ \*******************************************************************/
276+
277+ void convert_trans_to_netlistt::allocate_state_variables (netlistt &dest)
278+ {
279+ // we work with the sorted var_map to get a deterministic
280+ // allocation for the latches and inputs
281+
282+ for (auto var_map_it : dest.var_map .sorted ())
283+ {
284+ auto &var = var_map_it->second ;
285+
286+ for (auto &bit : var.bits )
287+ {
288+ // just initialize with something
289+ bit.current = const_literal (false );
290+ bit.next = const_literal (false );
291+
292+ if (var.is_input () || var.is_latch ())
293+ bit.current = dest.new_var_node ();
294+ }
295+ }
284296}
285297
286298/* ******************************************************************\
@@ -304,9 +316,10 @@ void convert_trans_to_netlistt::operator()(
304316 lhs_map.clear ();
305317 rhs_list.clear ();
306318 constraint_list.clear ();
307-
308- map_vars (module , dest);
309-
319+
320+ dest.var_map = build_var_map (module );
321+ allocate_state_variables (dest);
322+
310323 // setup lhs_map
311324
312325 for (var_mapt::mapt::iterator
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