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This PR introduces draft kernel implementations for the JTEC and JTEC+ engine controller families. Bootloader sections have been added, and placeholder TODO comments have been inserted where implementation is still pending. Register offsets are labeled but require renaming for consistency in future revisions. JTEC notes: - Flash and EEPROM command handlers are incomplete. - Flash programming requires a different algorithm than newer controllers. - EEPROM routines may be too large to run from RAM, due to the need to initialize the HC11K4 co-processor using a large static bootloader. Pending tasks: - Implement Flash algorithm - Investigate RAM constraints for EEPROM routine - Rename register offsets for backwards compatibility JTEC+ notes: - Flash programming algorithm is the same as SBEC3A. - EEPROM limitations are the same as JTEC. Pending tasks: - Reuse SBEC3A Flash algorithm (already done) - Evaluate EEPROM feasibility - Clean up register naming Resources: https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_erase_st.asm https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_write_st.asm https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_read_pn.asm (HC11K4 bootloader upload and start) https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_read_eeprom.asm https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_write_eeprom.asm https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtecplus/jtecplus_read_pn.asm (HC11K4 bootloader upload and start) https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtecplus/jtecplus_read_eeprom.asm https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtecplus/jtecplus_write_eeprom.asm Status: This is an early draft meant to establish structure and document hardware-specific constraints before full implementation. Further commits will follow to complete command logic and memory handling.
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This PR introduces draft kernel implementations for the JTEC (1996-1998) and JTEC+ (1999+) engine controller families. Bootloader sections have been added, and placeholder TODO comments have been inserted where implementation is still pending. Register offsets are labeled but require renaming for consistency in future revisions.
JTEC notes:
Pending tasks:
JTEC+ notes:
Pending tasks:
Resources:
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/hc16def.inc
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_erase_st.asm
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_write_st.asm
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_read_pn.asm (HC11K4 bootloader upload and start)
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_read_eeprom.asm
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtec/jtec_write_eeprom.asm
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtecplus/jtecplus_read_pn.asm (HC11K4 bootloader upload and start)
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtecplus/jtecplus_read_eeprom.asm
https://github.com/laszlodaniel/DRBProEmulator/blob/main/ESP32/ChryslerScanner/lib/sae_j2610_sci/boot/jtecplus/jtecplus_write_eeprom.asm
Status:
This is an early draft meant to establish structure and document hardware-specific constraints before full implementation. Further commits will follow to complete command logic and memory handling.