Skip to content

Conversation

@LH-and-FPGA
Copy link

The testpipeline.txt file was modified last year, but the ram file has not been updated accordingly.

@LH-and-FPGA
Copy link
Author

The STR R1 [...] is changed to STR R0 [...] last year:
image

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant