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This is missing a bunch of changes that will be needed to pass CI (see #578). |
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Cherry-picked from @drinkcat (Nicolas Boichat) esp-rs#578: - sleep: GPIO deep sleep wakeup API renames for v6.0 - lcd: DMA2D API change, pixel_format field removal, rgb_ele_order union change, RGB666 format removal, disp_off -> disp_on_off - uart: Clock source changes for v6 (PLL_F80M/PLL_F48M chip guards) - pcnt: Proper PCNT_CHANNELS_PER_UNIT const with alloc/heapless split, clk_src with actual enum value - timer: backup_before_sleep guard fix (removed in v6.0, not v6.1) - CI: Add v6.0 to test matrix with RUSTFLAGS handling Co-Authored-By: Nicolas Boichat <nicolas@boichat.ch> Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
Fixes ESP-IDF v6.0 API compatibility in esp-idf-hal. Purely additive -- no version bumps, no v4 removals. Incorporates all changes from @drinkcat's #578.
Companion PRs:
Changes (from @drinkcat's #578)
sleep: GPIO deep sleep wakeup API renames (
esp_deep_sleep_enable_gpio_wakeup->esp_sleep_enable_gpio_wakeup_on_hp_periph_powerdown, enum renames)lcd: DMA2D flag removed from
dpi_config.flags(now callesp_lcd_dpi_panel_enable_dma2d()after panel creation),pixel_formatfield removed fromesp_lcd_panel_dev_config_t,rgb_ele_orderunion change, RGB666 format dropped,esp_lcd_panel_disp_off->esp_lcd_panel_disp_on_offuart: Clock source Kconfig flags changed in v6 -- PLL_F80M and PLL_F48M now need chip-specific guards instead of relying on SOC capability flags
pcnt:
SOC_PCNT_CHANNELS_PER_UNITremoved -- proper const with alloc/heapless split.clk_srcfield uses actualPCNT_CLK_SRC_DEFAULTenum value.timer:
backup_before_sleepbitfield removed in v6.0 (was guarded for v6.1)CI: v6.0 added to test matrix, RUSTFLAGS updated
Breaking (v6.0 only)
Test plan