Try patching I2C for issues

.github/workflows/push.yml

@@ -25,7 +25,7 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        target: [esp32, esp32s2, esp32s3, esp32c2, esp32c3, esp32c6, esp32h2, esp32p4]
+        target: [esp32, esp32s2, esp32s3, esp32c2, esp32c3, esp32c6, esp32h2, esp32p4, esp32c5]
       fail-fast: false
     steps:
     - name: Checkout repository

configs/builds.json

@@ -4,7 +4,7 @@
 			"file":"libspi_flash.a",
 			"src":"build/esp-idf/spi_flash/libspi_flash.a",
 			"out":"lib/libspi_flash.a",
-			"targets":["esp32","esp32c2","esp32c3","esp32s2","esp32s3","esp32c6","esp32h2","esp32p4"]
+			"targets":["esp32","esp32c2","esp32c3","esp32s2","esp32s3","esp32c6","esp32h2","esp32p4","esp32c5"]
 		},
 		{
 			"file":"libesp_psram.a",
@@ -44,6 +44,20 @@
 		}
 	],
 	"targets":[
+		{
+			"target": "esp32c5",
+			"features":["qio_ram"],
+			"idf_libs":["qio","80m"],
+			"bootloaders":[
+				["qio","80m"],
+				["dio","80m"],
+				["qio","40m"],
+				["dio","40m"]
+			],
+			"mem_variants":[
+				["dio","80m"]
+			]
+		},
 		{
 			"target": "esp32p4",
 			"features":["qio_ram"],

configs/defconfig.esp32c5

@@ -0,0 +1,57 @@
+CONFIG_XTAL_FREQ_AUTO=y
+CONFIG_XTAL_FREQ=0
+CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
+CONFIG_SPIRAM=y
+
+CONFIG_BT_ENABLED=y
+CONFIG_BT_BLE_BLUFI_ENABLE=y
+CONFIG_RTC_CLK_CAL_CYCLES=576
+# CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 is not set
+CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304
+# This Enables RISCV LP for C6 - but it can't be used within Arduino at this time. 
+#CONFIG_ULP_COPROC_ENABLED=y
+#CONFIG_ULP_COPROC_LP_CORE=y
+#CONFIG_ULP_COPROC_RESERVE_MEM=4096
+
+#
+# OpenThread
+#
+CONFIG_OPENTHREAD_ENABLED=y
+# Border Router disabled
+# CONFIG_OPENTHREAD_BORDER_ROUTER=y
+# CONFIG_OPENTHREAD_RADIO_SPINEL_UART=y
+
+# DNS64 and NAT64 will be disabled for a while
+# OT IDF issue https://github.com/espressif/esp-idf/issues/15069
+# CONFIG_OPENTHREAD_DNS64_CLIENT=y
+
+# Radio for RPC
+# CONFIG_OPENTHREAD_RADIO=y 
+# CONFIG_OPENTHREAD_RADIO_NATIVE=y
+# CONFIG_OPENTHREAD_DIAG=n
+CONFIG_OPENTHREAD_COMMISSIONER=y
+CONFIG_OPENTHREAD_JOINER=y
+CONFIG_OPENTHREAD_CLI=y
+CONFIG_OPENTHREAD_SRP_CLIENT=y
+CONFIG_OPENTHREAD_DNS_CLIENT=y
+# Default dataset for quick start
+CONFIG_OPENTHREAD_NETWORK_NAME="OpenThread-ESP"
+CONFIG_OPENTHREAD_MESH_LOCAL_PREFIX="fd00:db8:a0:0::/64"
+CONFIG_OPENTHREAD_NETWORK_CHANNEL=15
+CONFIG_OPENTHREAD_NETWORK_PANID=0x1234
+CONFIG_OPENTHREAD_NETWORK_EXTPANID="dead00beef00cafe"
+CONFIG_OPENTHREAD_NETWORK_MASTERKEY="00112233445566778899aabbccddeeff"
+CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53"
+# end of OpenThread
+
+# Matter shall use only WiFi
+CONFIG_ENABLE_MATTER_OVER_THREAD=n
+
+#
+# Zigbee
+#
+CONFIG_ZB_ENABLED=y
+CONFIG_ZB_ZED=y
+CONFIG_ZB_RADIO_NATIVE=y
+# end of Zigbee

main/idf_component.yml

@@ -20,4 +20,4 @@ dependencies:
     version: "1.4.1"
     require: public
     rules:
-      - if: "target not in [esp32c2, esp32h2, esp32p4]"
+      - if: "target not in [esp32c2, esp32h2, esp32p4, esp32c5]"

patches/0001-fix-i2c-optimization-performance-on-esp32.diff

@@ -0,0 +1,124 @@
+diff --git a/components/esp_driver_i2c/i2c_master.c b/components/esp_driver_i2c/i2c_master.c
+index 8859998eb4..c2571f3d0d 100644
+--- a/components/esp_driver_i2c/i2c_master.c
++++ b/components/esp_driver_i2c/i2c_master.c
+@@ -197,22 +197,7 @@ static bool s_i2c_write_command(i2c_master_bus_handle_t i2c_master, i2c_operatio
+     i2c_ll_master_write_cmd_reg(hal->dev, hw_cmd, i2c_master->cmd_idx);
+     portEXIT_CRITICAL_SAFE(&handle->spinlock);
+     i2c_master->w_r_size = data_fill;
+-#if SOC_I2C_STOP_INDEPENDENT
+-    i2c_ll_master_write_cmd_reg(hal->dev, hw_end_cmd, i2c_master->cmd_idx + 1);
+-    i2c_master->cmd_idx = 0;
+-    if (i2c_master->i2c_trans.ops[i2c_master->trans_idx].total_bytes == i2c_master->i2c_trans.ops[i2c_master->trans_idx].bytes_used) {
+-        i2c_master->i2c_trans.cmd_count--;
+-        i2c_master->trans_idx++;
+-    }
+-    portENTER_CRITICAL_SAFE(&handle->spinlock);
+-    if (i2c_master->async_trans == false) {
+-        i2c_hal_master_trans_start(hal);
+-    } else {
+-        i2c_master->async_break = true;
+-    }
+-    portEXIT_CRITICAL_SAFE(&handle->spinlock);
+
+-#else
+     // If data cannot be sent in one time, send data out. Otherwise, continue configuring command.
+     if ((remaining_bytes - data_fill) != 0) {
+         portENTER_CRITICAL_SAFE(&handle->spinlock);
+@@ -252,7 +237,6 @@ static bool s_i2c_write_command(i2c_master_bus_handle_t i2c_master, i2c_operatio
+             }
+         }
+     }
+-#endif
+     *fifo_fill = data_fill;
+
+     return i2c_master->async_break;
+@@ -287,7 +271,6 @@ static bool s_i2c_read_command(i2c_master_bus_handle_t i2c_master, i2c_operation
+     hw_cmd.byte_num = *fifo_fill;
+
+     i2c_master->contains_read = true;
+-#if !SOC_I2C_STOP_INDEPENDENT
+     if (remaining_bytes < I2C_FIFO_LEN(i2c_master->base->port_num) - 1) {
+         if (i2c_operation->hw_cmd.ack_val == I2C_ACK_VAL) {
+             if (remaining_bytes != 0) {
+@@ -328,29 +311,6 @@ static bool s_i2c_read_command(i2c_master_bus_handle_t i2c_master, i2c_operation
+         }
+         portEXIT_CRITICAL_SAFE(&handle->spinlock);
+     }
+-#else
+-    portENTER_CRITICAL_SAFE(&handle->spinlock);
+-    // If the read command work with ack_val, but no bytes to read, we skip
+-    // this command, and run next command directly.
+-    if (hw_cmd.ack_val == I2C_ACK_VAL) {
+-        if (i2c_operation->total_bytes == 0) {
+-            i2c_master->trans_idx++;
+-            hw_cmd = i2c_master->i2c_trans.ops[i2c_master->trans_idx].hw_cmd;
+-            i2c_master->i2c_trans.cmd_count--;
+-        }
+-    }
+-    i2c_ll_master_write_cmd_reg(hal->dev, hw_cmd, i2c_master->cmd_idx);
+-    i2c_ll_master_write_cmd_reg(hal->dev, hw_end_cmd, i2c_master->cmd_idx + 1);
+-    portEXIT_CRITICAL_SAFE(&handle->spinlock);
+-    atomic_store(&i2c_master->status, I2C_STATUS_READ);
+-    portENTER_CRITICAL_SAFE(&handle->spinlock);
+-    if (i2c_master->async_trans == false) {
+-        i2c_hal_master_trans_start(hal);
+-    } else {
+-        i2c_master->async_break = true;
+-    }
+-    portEXIT_CRITICAL_SAFE(&handle->spinlock);
+-#endif
+
+     return i2c_master->async_break;
+ }
+@@ -679,9 +639,7 @@ I2C_MASTER_ISR_ATTR static void i2c_isr_receive_handler(i2c_master_bus_t *i2c_ma
+             i2c_operation->bytes_used = 0;
+         }
+         portEXIT_CRITICAL_ISR(&i2c_master->base->spinlock);
+-    }
+-#if !SOC_I2C_STOP_INDEPENDENT
+-    else {
++    } else {
+         i2c_operation_t *i2c_operation = &i2c_master->i2c_trans.ops[i2c_master->read_buf_pos];
+         portENTER_CRITICAL_ISR(&i2c_master->base->spinlock);
+         i2c_ll_read_rxfifo(hal->dev, i2c_operation->data + i2c_operation->bytes_used, i2c_master->read_len_static);
+@@ -693,7 +651,6 @@ I2C_MASTER_ISR_ATTR static void i2c_isr_receive_handler(i2c_master_bus_t *i2c_ma
+         i2c_master->contains_read = false;
+         portEXIT_CRITICAL_ISR(&i2c_master->base->spinlock);
+     }
+-#endif
+ }
+
+ static void i2c_master_isr_handler_default(void *arg)
+diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+index 0ba999f747..22c2c0a407 100644
+--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
++++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+@@ -391,10 +391,6 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
+     bool
+     default y
+
+-config SOC_I2C_STOP_INDEPENDENT
+-    bool
+-    default y
+-
+ config SOC_I2S_NUM
+     int
+     default 2
+diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
+index 1937908170..f7f4c16949 100644
+--- a/components/soc/esp32/include/soc/soc_caps.h
++++ b/components/soc/esp32/include/soc/soc_caps.h
+@@ -208,9 +208,6 @@
+ #define SOC_I2C_SUPPORT_APB     (1)
+ #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
+
+-// On ESP32, the stop bit should be independent, we can't put trans data and stop command together
+-#define SOC_I2C_STOP_INDEPENDENT (1)
+-
+ /*-------------------------- I2S CAPS ----------------------------------------*/
+ // ESP32 has 2 I2S
+ #define SOC_I2S_NUM                 (2U)
+-- 
+2.39.5 (Apple Git-154)
+

tools/config.sh

@@ -6,11 +6,11 @@ if [ -z $IDF_PATH ]; then
 fi
 
 if [ -z $IDF_BRANCH ]; then
-    IDF_BRANCH="release/v5.4"
+    IDF_BRANCH="master"
 fi
 
 if [ -z $AR_PR_TARGET_BRANCH ]; then
-    AR_PR_TARGET_BRANCH="master"
+    AR_PR_TARGET_BRANCH="release/v3.3.x"
 fi
 
 if [ -z $IDF_TARGET ]; then

tools/gen_pioarduino_manifest.py

@@ -23,6 +23,9 @@ def convert_version(version_string):
     'v7.7.7' becomes '7.7.7'
     """
 
+    if version_string == 'heads/master':
+        return ".".join(("5", "5", "0")) #temporary
+
     regex_pattern = (
         r"v(?P<MAJOR>0|[1-9]\d*)\.(?P<MINOR>0|[1-9]\d*)\.*(?P<PATCH>0|[1-9]\d*)*"
     )

tools/install-esp-idf.sh

@@ -37,10 +37,10 @@ if [ ! -x $idf_was_installed ] || [ ! -x $commit_predefined ]; then
 	export IDF_COMMIT=$(git -C "$IDF_PATH" rev-parse --short HEAD)
 	export IDF_BRANCH=$(git -C "$IDF_PATH" symbolic-ref --short HEAD || git -C "$IDF_PATH" tag --points-at HEAD)
 
-	# Temporarily patch the ESP32-S2 I2C LL driver to keep the clock source
 	cd $IDF_PATH
-	patch -p1 -N -i $AR_PATCHES/esp32s2_i2c_ll_master_init.diff
-	patch -p1 -N -i $AR_PATCHES/lwip_max_tcp_pcb.diff
+	# Temporarily patch the ESP32-S2 I2C LL driver to keep the clock source
+	#patch -p1 -N -i $AR_PATCHES/esp32s2_i2c_ll_master_init.diff
+	patch -p1 -N -i $AR_PATCHES/0001-fix-i2c-optimization-performance-on-esp32.diff
 	cd -
 fi