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141,030 changes: 10,816 additions & 130,214 deletions fboss/agent/platforms/common/blackwolf800banw/Blackwolf800banwPlatformMapping.cpp

Large diffs are not rendered by default.

Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,10 @@ class Blackwolf800banwPlatformMapping : public PlatformMapping {
Blackwolf800banwPlatformMapping();
explicit Blackwolf800banwPlatformMapping(
const std::string& platformMappingStr);
// For CPU system port number as key, get the core for CPU port and
// the port ID within the core.
virtual std::map<uint32_t, std::pair<uint32_t, uint32_t>>
getCpuPortsCoreAndPortIdx() const override;

private:
// Forbidden copy constructor and assignment operator
Expand Down
14 changes: 11 additions & 3 deletions fboss/agent/test/utils/ConfigUtils.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -58,9 +58,15 @@ int getRdswSysPortBlockSize(
// For dual stage 3/2q mode, sys ports are allocated in 2 blocks of 28 while
// for single state we allocate a single block of 44
// For PLATFORM_JANGA800BIC, use Prod range
if (platformType.has_value() &&
platformType.value() == PlatformType::PLATFORM_JANGA800BIC) {
return 22;
if (platformType.has_value()) {
switch (platformType.value()) {
case PlatformType::PLATFORM_JANGA800BIC:
return 22;
case PlatformType::PLATFORM_BLACKWOLF800BANW:
return 1024;
default:
break;
}
}
return isDualStage3Q2QMode() ? 28 : 44;
}
Expand Down Expand Up @@ -488,6 +494,8 @@ cfg::DsfNode dsfNodeConfig(
return PlatformType::PLATFORM_MERU400BFU;
case cfg::AsicType::ASIC_TYPE_RAMON3:
return PlatformType::PLATFORM_MERU800BFA;
case cfg::AsicType::ASIC_TYPE_Q4D:
return PlatformType::PLATFORM_BLACKWOLF800BANW;
default:
break;
}
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