[Celestica] Tahansb800bc: Update SI settings

[lihua-cls]

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Summary

Update tahansb800bc SI Settings to use fixed value below:

Backplane: 0,0,-40,128,0,0,0 with ER mode and Precoding enabled
OSFP 200G: 0,0,-4,144,0,0,0
OSFP 100G: 0,0,-28,136,0,0,0
Mgmt(QSFP28): 0,0,3,31,19,0,0

Note:

• The test were performed with test Vehicle;
• To use fixed SI settings, link training should be disabled in the embedded yml file by setting: "LINK_TRAINING 0";
• For Backplane ports, ER mode and Precoding should also be enabled;
• To bypass a known issue that only last lane was succesfully set to ER mode when setting multiple lanes port (ref: https://brcmsemiconductor-csm.wolkenservicedesk.com/wolken-support/mycases/request-details?requestId=12445175 ), the embedded yml in json config file should be set to "ENABLE 1";
• The diff also changed the media type to BACKPLANE for front panel ports.

Test Plan

Ports can be up in fboss and SDK

(unidiag)[root@localhost fboss]# ./bin/fboss2 show port

 ID  Name      AdminState  LinkState  ActiveState  Transceiver  TcvrID  Speed  ProfileID                             HwLogicalPortId  Drained  PeerSwitchDrained  PeerPortDrainedOrDown  Errors  Core Id  Virtual device Id  Cable Len meters 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 1   eth1/1/1  Enabled     Up         --           Present      0       800G   PROFILE_800G_4_PAM4_RS544X2N_OPTICAL  504              No       --                 --                     --      --       --                 --               
 5   eth1/1/5  Enabled     Up         --           Present      0       800G   PROFILE_800G_4_PAM4_RS544X2N_OPTICAL  505              No       --                 --                     --      --       --                 --               
 ...
 65  eth1/9/1  Enabled     Up         --           Present      8       100G   PROFILE_100G_4_NRZ_RS528_OPTICAL      268              No       --                 --                     --      --       --                 --               
 ...
 66   eth1/10/1  Enabled     Up         --                        0       400G   PROFILE_400G_2_PAM4_RS544X2N_COPPER  1                No       --                 --                     --      --       --                 --               
 68   eth1/10/3  Enabled     Up         --                        0       400G   PROFILE_400G_2_PAM4_RS544X2N_COPPER              
...

drivshell>ps
ps

              ena/        speed/ link auto    STP                  lrn             max    cut                 loop
        port  link  Lns   duplex scan neg?   state   pause  discrd ops   medium  frame   thru            FEC  back
    cd0(  1)  up     2  400G  FD   SW  No   Forward          None   FA Backplane  9412   No   RS544-2xN-IEEE      
    cd1(  2)  up     2  400G  FD   SW  No   Forward          None   FA Backplane  9412   No   RS544-2xN-IEEE      
...

dsc output example:

 condor3_pc_phy_pmd_info_dump:588 type = 16384 laneMask  = 0x3

**** SERDES DISPLAY DIAG DATA ****
Rev ID Letter        = 00
Rev ID Process       = 02
Rev ID Model         = 1F
Rev ID 2             = 01
Rev ID # Lanes       = 8
Core  = 0;    LANE  = 0
SERDES API Version   = A00110
Common Ucode Version = E001_1A
AFE Hardware Version = 0xA0
SerDes type          = condor3_pc
FLR supported        = 0x1
lane_select          = 0x3


Passed timestamp check : Lane 0:uC timestamp: 40044Resolution: 10.0us/count. Passing resolution limits:Max: 11.2us/countMin: 8.8us/count
SerDes type = condor3_pc
CORE RST_ST  PLL_PWDN  UC_ATV   COM_CLK   UCODE_VER  API_VER  AFE_VER   LIVE_TEMP   AVG_TMON   RESCAL  2xVCO_RATE ANA_VCO_RANGE  PLL_DIV  PLL_LOCK
 00   0,00      0        1     156.25MHz   E001_1A   A00110     0xA0       59C      (13) 59C    0x07   106.25GHz     067         170        1   

LN (P RX  , CDRxN , UC_CFG,   UC_STS,  RST, STP) SD LCK RXPPM PF(M,L,H) VGA  DCO  TP(0,1,2)      RXFFE(n3,n2,n1,m,p1,p2)      DFE(1,2)  FLT(M,S) TXPPM        TXEQ(n3,n2,n1,m,p1,p2) NLC(U,L)    EYE(U,M,L)  LINK_TIME  SNR     BER
 0 (-+P4E ,BRx1:x1, 0x5400, 0x00_0000, 0,0, 41 ) 1  1*    0  (14,22,12)  55    9 ( 0,39, 0) ( 145,-127,   43, 326,   41, 152)  ( x, 0) (  8, 42)    0    P (  0,  0,-40,128,  0,  0)( +0, +0) ( 60, 58, 60)  2006.4    20.66  !chk_en 
 1 (+-P4E ,BRx1:x1, 0x5400, 0x00_0000, 0,0, 41 ) 1  1*    0  (14,22,12)  51    4 ( 0,39, 0) ( 140,-118,   31, 328,   43, 132)  ( x, 0) (  8, 45)    0    P (  0,  0,-40,128,  0,  0)( +0, +0) ( 62, 60, 60)  1754.8    20.81  !chk_en 

**** SERDES DISPLAY DIAG DATA END ****

Sanity test some link test cases passed:

[       OK ] cold_boot.AgentEnsembleLinkTest.ecmpShrink (88951 ms)
[       OK ] cold_boot.AgentEnsembleLinkTest.asicLinkFlap (150360 ms)
[       OK ] cold_boot.AgentEnsembleLinkTest.getTransceivers (87704 ms)
[       OK ] cold_boot.AgentEnsembleLinkTest.trafficRxTx (82495 ms)
[       OK ] cold_boot.AgentEnsembleLinkTest.opticsTxDisableRandomPorts (139672 ms)
[       OK ] cold_boot.AgentEnsembleLinkTest.opticsTxDisableEnable (125544 ms)
[       OK ] cold_boot.AgentEnsembleLinkTest.qsfpColdbootAfterAgentUp (124321 ms)
[       OK ] cold_boot.AgentEnsembleLinkTest.iPhyInfoTest (112124 ms)
[       OK ] cold_boot.AgentEnsembleLinkTest.clearIphyInterfaceCounters (113085 ms)
[       OK ] cold_boot.AgentEnsembleEmptyLinkTest.CheckInit (91691 ms)
[       OK ] cold_boot.AgentFabricLinkTest.linkActiveAndLoopStatus (92820 ms)

Full log put in Gdrive

[meta-codesync]

@ashutoshgrewal has imported this pull request. If you are a Meta employee, you can view this in D95078738.

[togthoma]

@lihua-cls Does the SI settings are derived with NIC connection or its with loopback on test fixture?

[lihua-cls]

@lihua-cls Does the SI settings are derived with NIC connection or its with loopback on test fixture?

Hi @togthoma
Did you mean backplane ports right? The SI settings for backplane ports were derived with loopback on test fixture.

Thanks