Merge pull request #1 from alex-yang-upenn/integ_vitis_accel_dev

First Step Towards Integration

Author: axiotisk

hls4ml/backends/vitis_accelerator/supported_boards.json

@@ -0,0 +1,26 @@
+{
+    "alveo-u55c": {
+      "board_type": "alveo",
+      "part": "xcu55c-fsvh2892-2L-e",
+      "platform": "xilinx_u55c_gen3x16_xdma_3_202210_1",
+      "memory": {"type": "hbm", "channels": 32, "capacity": 16}
+    },
+    "alveo-u50": {
+      "board_type": "alveo",
+      "part": "xcu50-fsvh2104-2-e",
+      "platform": "xilinx_u50_gen3x16_xdma_5_202210_1",
+      "memory": {"type": "hbm", "channels": 32, "capacity": 8}
+    },
+    "alveo-u250": {
+      "board_type": "alveo",
+      "part": "xcu250-figd2104-2L-e",
+      "platform": "xilinx_u250_xdma_201830_2",
+      "memory": {"type": "ddr", "channels": 4, "capacity": 64}
+    },
+    "vck5000": {
+      "board_type": "versal",
+      "part": "xcvc1902-2msevsvd1760", 
+      "platform": "xilinx_vck5000_gen4x8_qdma_2_202220_1",
+      "memory":{"type": "ddr", "channels": 3, "capacity": 12}
+    }
+  }

hls4ml/backends/vitis_accelerator/vitis_accelerator_backend.py

@@ -1,3 +1,7 @@
+import os
+import sys
+import subprocess
+
 from hls4ml.backends import VitisBackend, VivadoBackend
 from hls4ml.model.flow import get_flow, register_flow
 
@@ -8,38 +12,15 @@ def __init__(self):
         self._register_layer_attributes()
         self._register_flows()
 
-    def _register_flows(self):
-        validation_passes = [
-            'vitisaccelerator:validate_conv_implementation',
-            'vitisaccelerator:validate_strategy',
-        ]
-        validation_flow = register_flow('validation', validation_passes, requires=['vivado:init_layers'], backend=self.name)
-
-        # Any potential templates registered specifically for Vitis backend
-        template_flow = register_flow(
-            'apply_templates', self._get_layer_templates, requires=['vivado:init_layers'], backend=self.name
-        )
-
-        writer_passes = ['make_stamp', 'vitisaccelerator:write_hls']
-        self._writer_flow = register_flow('write', writer_passes, requires=['vitis:ip'], backend=self.name)
-
-        ip_flow_requirements = get_flow('vivado:ip').requires.copy()
-        ip_flow_requirements.insert(ip_flow_requirements.index('vivado:init_layers'), validation_flow)
-        ip_flow_requirements.insert(ip_flow_requirements.index('vivado:apply_templates'), template_flow)
-
-        self._default_flow = register_flow('ip', None, requires=ip_flow_requirements, backend=self.name)
-
     def create_initial_config(
         self,
-        board='pynq-z2',
+        board='alveo-u55c',
         part=None,
         clock_period=5,
         io_type='io_parallel',
-        interface='axi_stream',
-        driver='python',
-        input_type='float',
-        output_type='float',
-        platform='xilinx_u250_xdma_201830_2',
+        num_kernel=1,
+        num_thread=1,
+        batchsize=8192
     ):
         '''
         Create initial accelerator config with default parameters
@@ -48,32 +29,66 @@ def create_initial_config(
             board: one of the keys defined in supported_boards.json
             clock_period: clock period passed to hls project
             io_type: io_parallel or io_stream
-            interface: `axi_stream`: generate hardware designs and drivers which exploit axi stream channels.
-                       `axi_master`: generate hardware designs and drivers which exploit axi master channels.
-                       `axi_lite` : generate hardware designs and drivers which exploit axi lite channels. (Don't use it
-                       to exchange large amount of data)
-            driver: `python`: generates the python driver to use the accelerator in the PYNQ stack.
-                    `c`: generates the c driver to use the accelerator bare-metal.
-            input_type: the wrapper input precision. Can be `float` or an `ap_type`. Note: VivadoAcceleratorBackend
-                             will round the number of bits used to the next power-of-2 value.
-            output_type: the wrapper output precision. Can be `float` or an `ap_type`. Note:
-                              VivadoAcceleratorBackend will round the number of bits used to the next power-of-2 value.
-            platform: development target platform
-
+            num_kernel: how many compute units to create on the fpga
+            num_thread: how many threads the host cpu uses to drive the fpga
         Returns:
             populated config
         '''
-        board = board if board is not None else 'pynq-z2'
+        board = board if board is not None else 'alveo-u55c'
         config = super().create_initial_config(part, clock_period, io_type)
         config['AcceleratorConfig'] = {}
         config['AcceleratorConfig']['Board'] = board
-        config['AcceleratorConfig']['Interface'] = interface  # axi_stream, axi_master, axi_lite
-        config['AcceleratorConfig']['Driver'] = driver
-        config['AcceleratorConfig']['Precision'] = {}
-        config['AcceleratorConfig']['Precision']['Input'] = {}
-        config['AcceleratorConfig']['Precision']['Output'] = {}
-        config['AcceleratorConfig']['Precision']['Input'] = input_type  # float, double or ap_fixed<a,b>
-        config['AcceleratorConfig']['Precision']['Output'] = output_type  # float, double or ap_fixed<a,b>
-        config['AcceleratorConfig']['Platform'] = platform
-
+        config['AcceleratorConfig']['Num_Kernel'] = num_kernel
+        config['AcceleratorConfig']['Num_Thread'] = num_thread
+        config['AcceleratorConfig']['Batchsize'] = batchsize
         return config
+
+    def build(self, model, target="all"):
+        if 'linux' in sys.platform:
+            if 'XILINX_VITIS' not in os.environ:
+                raise Exception("XILINX_VITIS environmental variable missing. Please install XRT and Vitis, and run the setup scripts before building")
+            if 'XILINX_XRT' not in os.environ:
+                raise Exception("XILINX_XRT environmental variable missing. Please install XRT and Vitis, and run the setup scripts before building")
+            if 'XILINX_VIVADO' not in os.environ:
+                raise Exception("XILINX_VIVADO environmental variable missing. Please install XRT and Vitis, and run the setup scripts before building")
+
+            if target not in ["all", "host", "hls", "xclbin"]:
+                raise Exception("Invalid build target")
+
+            curr_dir = os.getcwd()
+            os.chdir(model.config.get_output_dir())
+            command = "make " + target
+            # Pre-loading libudev
+            ldconfig_output = subprocess.check_output(["ldconfig", "-p"]).decode("utf-8")
+            for line in ldconfig_output.split("\n"):
+                if "libudev.so" in line and "x86" in line:
+                    command = "LD_PRELOAD=" + line.split("=>")[1].strip() + " " + command
+                    break
+            os.system(command)
+            os.chdir(curr_dir)
+        else:
+            raise Exception("Currently untested on non-Linux OS")
+
+    def predict(self, model, x):
+        raise Exception("TODO: Needs to be implemented")
+
+    def _register_flows(self):
+        validation_passes = [
+            'vitisaccelerator:validate_conv_implementation',
+            'vitisaccelerator:validate_strategy',
+        ]
+        validation_flow = register_flow('validation', validation_passes, requires=['vivado:init_layers'], backend=self.name)
+
+        # Any potential templates registered specifically for Vitis backend
+        template_flow = register_flow(
+            'apply_templates', self._get_layer_templates, requires=['vivado:init_layers'], backend=self.name
+        )
+
+        writer_passes = ['make_stamp', 'vitisaccelerator:write_hls']
+        self._writer_flow = register_flow('write', writer_passes, requires=['vitis:ip'], backend=self.name)
+
+        ip_flow_requirements = get_flow('vivado:ip').requires.copy()
+        ip_flow_requirements.insert(ip_flow_requirements.index('vivado:init_layers'), validation_flow)
+        ip_flow_requirements.insert(ip_flow_requirements.index('vivado:apply_templates'), template_flow)
+
+        self._default_flow = register_flow('ip', None, requires=ip_flow_requirements, backend=self.name)

hls4ml/backends/vitis_accelerator/vitis_accelerator_config.py

@@ -1,10 +1,54 @@
+import json
+import os
+
 class VitisAcceleratorConfig:
     def __init__(self, config):
         self.config = config.config
+        accel_config = self.config.get('AcceleratorConfig', None)
+        if accel_config is None:
+             raise Exception('Missing AcceleratorConfig')
+        
+        self.board = accel_config.get('Board', 'alveo-u55c')
+        self.supported_boards = json.load(open(os.path.dirname(__file__) + '/supported_boards.json'))
+        if self.board in self.supported_boards.keys():
+            board_info = self.supported_boards[self.board]
+            self.board_type = board_info['board_type']
+            self.part = board_info['part']
+            self.platform = board_info['platform']
+            self.memory_type = board_info['memory']['type']
+            self.memory_channel_count = board_info['memory']['channels']
+        else:
+            raise Exception('The board does not appear in supported_boards.json file')
+
+        if self.config.get('Part') is not None:
+            if self.config.get('Part') != self.part:
+                print(
+                    'WARNING: You set a Part that does not correspond to the Board you specified.' 
+                    'The correct Part is now set.'
+                )
+                self.config['Part'] = self.part
+        
+        self.num_kernel = accel_config.get('Num_Kernel')
+        self.num_thread = accel_config.get('Num_Thread')
+        self.batchsize = accel_config.get('Batchsize')        
 
-        self.platform = self.config['AcceleratorConfig'].get(
-            'Platform', 'xilinx_u250_xdma_201830_2'
-        )  # Get platform folder name
+    def get_board_type(self):
+        return self.board_type
 
     def get_platform(self):
         return self.platform
+    
+    def get_num_thread(self):
+        return self.num_thread
+    
+    def get_num_kernel(self):
+        return self.num_kernel
+    
+    def get_batchsize(self):
+        return self.batchsize
+    
+    def get_memory_type(self):
+        return self.memory_type
+    
+    def get_memory_channel_count(self):
+        return self.memory_channel_count

hls4ml/model/graph.py

@@ -734,6 +734,9 @@ def _compute_n_samples(self, x):
         return int(n_sample)
 
     def predict(self, x):
+        if self.config.config.get('Backend', 'Vivado') == 'VitisAccelerator':
+            return self.config.backend.predict(self, x)
+
         top_function, ctype = self._get_top_function(x)
         n_samples = self._compute_n_samples(x)
         n_inputs = len(self.get_input_variables())

hls4ml/templates/vitis_accelerator/Makefile

@@ -1,32 +1,58 @@
-.PHONY: clean
-
-PLATFORM=myplatform
+# Absolute path to top directory of accelerator project
+PWD = $(shell readlink -f .)
 
-app.exe: ./myproject_host.cpp
-	g++ -g -std=c++14 ./myproject_host.cpp -o app.exe \
-		-I firmware/ap_types -I/opt/xilinx/xrt/include \
-		-L${XILINX_XRT}/lib/ -lxrt_coreutil -lOpenCL -pthread -lrt -lstdc++
+# Checks for XILINX_VITIS
+ifndef XILINX_VITIS
+$(error XILINX_VITIS variable is not set, please set correctly and rerun)
+endif
 
-myproject_kernel.xo: myproject_kernel.cpp
-	v++ --target hw --compile -I"./" --config accelerator_card.cfg -o"build/myproject_kernel.xo" "myproject_kernel.cpp"
+# Checks for XILINX_XRT
+ifndef XILINX_XRT
+$(error XILINX_XRT variable is not set, please set correctly and rerun)
+endif
 
-ifneq (,$(findstring vck5000,$(PLATFORM)))
-myproject_kernel.xsa: ./build/myproject_kernel.xo
-	v++ -l -t hw --config ./accelerator_card.cfg ./build/myproject_kernel.xo -o myproject_kernel.xsa
+# Checks for XILINX_VIVADO
+ifndef XILINX_VIVADO
+$(error XILINX_VIVADO variable is not set, please set correctly and rerun)
+endif
 
-myproject_kernel.xclbin: ./myproject_kernel.xsa
-	v++ --package -t hw --config ./accelerator_card.cfg ./myproject_kernel.xsa -o myproject_kernel.xclbin
-else
-myproject_kernel.xclbin: ./myproject_kernel.xo
-	v++ -l -t hw --config ./accelerator_card.cfg ./build/myproject_kernel.xo -o myproject_kernel.xclbin
+# Checks for g++
+ifneq ($(shell expr $(shell g++ -dumpversion) \>= 5), 1)
+CXX := $(XILINX_VIVADO)/tps/lnx64/gcc-6.2.0/bin/g++
+$(warning [WARNING]: g++ version older. Using g++ provided by the tool : $(CXX))
 endif
 
-emconfig.json:
-	emconfigutil --platform  xilinx_vck5000_gen4x8_qdma_2_202220_1 --nd 1
+KERN_LIBRARIES += -I./ -I./firmware/ -I./firmware/weights -I./firmware/nnet_utils/
 
-clean:
-	rm -f KERAS_3layer.json KERAS_3layer_weights.h5  prj_tuto_vitis_stream.tar.gz
-	rm -rf myproject_kernel* myproject_kernel* .exe *json *csv *log *summary _x xilinx* .run .Xil .ipcache *.jou
+.PHONY: all
+all: host xclbin
+
+# Building kernel
+./build/myproject_kernel.xo: kernel_wrapper.cpp
+	mkdir -p ./build && mkdir -p ./build/xo
+	v++ -c -t hw --config ./accelerator_card.cfg --temp_dir build/xo kernel_wrapper.cpp firmware/myproject.cpp -o ./build/myproject_kernel.xo $(KERN_LIBRARIES)
 
-# Unless specified, use the current directory name as the v++ build target
-TARGET ?= $(notdir $(CURDIR))
+# hls-fpga-machine-learning packaging 
+
+# Building Host 
+INCLUDES += -I$(XILINX_XRT)/include/ -I$(XILINX_VIVADO)/include/ -I$(XILINX_HLS)/include/ \
+			-I$(PWD)/libs/ -I$(PWD)/firmware/ -I$(PWD)/firmware/nnet_utils/
+CXXFLAGS += -Wall -std=c++11 -Wno-unknown-pragmas -g -O0 
+LDFLAGS = -L$(XILINX_XRT)/lib/ -lstdc++ -lpthread -lrt -lOpenCL
+
+host: myproject_host_cl.cpp libs/xcl2.cpp
+	$(CXX) $(CXXFLAGS) $^ -o $@ $(INCLUDES) $(LDFLAGS) 
+
+.PHONY: hls
+hls: ./build/myproject_kernel.xo
+
+.PHONY: xclbin
+xclbin: ./build/kernel_wrapper.xclbin
+
+# Cleaning stuff
+.PHONY: clean
+clean:
+	-rm -rf host
+	-rm -rf *.xclbin*
+	-rm -rf build*
+	-rm -rf *.log *.jou *.rpt *.csv *.mdb *.ltx

hls4ml/templates/vitis_accelerator/accelerator_card.cfg

@@ -1,10 +1,26 @@
-platform=myplatform
+kernel=kernel_wrapper
+messageDb=build/kernel_wrapper.mdb
+platform=MYPLATFORM
 save-temps=1
-kernel=myproject_kernel
-messageDb=build/myproject_kernel.mdb
-temp_dir=build
-report_dir=build/reports
-log_dir=build/logs
 
 [advanced]
-misc=solution_name=myproject_kernel
+prop=kernel.kernel_wrapper.kernel_flags=-std=c++11
+
+[hls]
+pre_tcl=./hls_config.tcl
+
+# hls-fpga-machine-learning kernel control
+
+[vivado]
+prop=run.impl_1.STEPS.OPT_DESIGN.IS_ENABLED=true
+prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=Explore
+
+prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=AltSpreadLogic_high
+
+prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true
+prop=run.imp1_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
+
+prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore
+
+prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true
+prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore

hls4ml/templates/vitis_accelerator/hls_config.tcl

@@ -0,0 +1,2 @@
+config_interface -m_axi_auto_max_ports=true
+config_interface -m_axi_offset slave

hls4ml/templates/vitis_accelerator/kernel_wrapper.h

@@ -0,0 +1,10 @@
+#ifndef KERNEL_WRAPPER_H
+#define KERNEL_WRAPPER_H
+
+#include "firmware/defines.h"
+
+// hls-fpga-machine-learning accelerator parameters
+
+// hls-fpga-machine-learning accelerator io
+
+#endif