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@bchalios bchalios commented Sep 2, 2025

This is the first in a series of PRs that are meant to simplify our PCI codebase

Changes

Mainly two changes:

  • Move (de)allocation of the BAR outside the PciDevice trait
  • Encode in the PCI handling logic the fact that we only ever create 64-bit BAR regions with fixed size (for VirtIO) devices

Reason

A lot of the PCI code we pulled from Cloud Hypervisor is built in the form of a library trying to be generic and support various functionalities of the PCI specification.a

In our case, we only support certain functionality. For example, we only have two types of PCI devices, VirtIO devices and the Root Port. Only VirtIO devices use BAR regions (64 bits). We don't use 32-bit, I/O or ROM BARs.

We'd like to move towards a PCI implementation which is tailored to our use-case instead of a generic library implementation.

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  • I have read and understand CONTRIBUTING.md.
  • I have run tools/devtool checkbuild --all to verify that the PR passes
    build checks on all supported architectures.
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  • I have described what is done in these changes, why they are needed, and
    how they are solving the problem in a clear and encompassing way.
  • I have updated any relevant documentation (both in code and in the docs)
    in the PR.
  • I have mentioned all user-facing changes in CHANGELOG.md.
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  • When making API changes, I have followed the
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  • This functionality cannot be added in rust-vmm.

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codecov bot commented Sep 2, 2025

Codecov Report

❌ Patch coverage is 95.48872% with 6 lines in your changes missing coverage. Please review.
✅ Project coverage is 82.79%. Comparing base (81c698a) to head (bbe0427).
⚠️ Report is 5 commits behind head on main.

Files with missing lines Patch % Lines
src/pci/src/configuration.rs 97.82% 2 Missing ⚠️
src/vmm/src/device_manager/pci_mngr.rs 77.77% 2 Missing ⚠️
src/vmm/src/devices/virtio/transport/pci/device.rs 93.75% 2 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##             main    #5426      +/-   ##
==========================================
+ Coverage   82.68%   82.79%   +0.11%     
==========================================
  Files         263      263              
  Lines       27478    27301     -177     
==========================================
- Hits        22719    22603     -116     
+ Misses       4759     4698      -61     
Flag Coverage Δ
5.10-m5n.metal 82.97% <95.48%> (+0.12%) ⬆️
5.10-m6a.metal 82.22% <95.48%> (+0.12%) ⬆️
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6.1-m5n.metal 83.01% <95.48%> (+0.12%) ⬆️
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6.1-m6g.metal 79.57% <95.48%> (+0.10%) ⬆️
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@bchalios bchalios marked this pull request as ready for review September 2, 2025 12:19
@bchalios bchalios enabled auto-merge (rebase) September 2, 2025 12:19
@bchalios bchalios self-assigned this Sep 2, 2025
@bchalios bchalios added the Status: Awaiting review Indicates that a pull request is ready to be reviewed label Sep 2, 2025
@bchalios bchalios force-pushed the pci_refactoring branch 3 times, most recently from ebc9a7a to 1fe2da9 Compare September 5, 2025 13:16
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ShadowCurse previously approved these changes Sep 5, 2025
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I think we should understand what is the trade-off between keeping with future-proof logic in the code or remove it altogether and add it back if in the future we add support for vfio.
Also, I dislike the use of asserts in library code, which makes it more coupled with the code itself. I think error handling should be done in the binary crate. But this is a stylistic preference, I wouldn't block the CR on this right now. This will however hinder any upstreaming efforts in the future, if any.

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bchalios commented Sep 8, 2025

I think we should understand what is the trade-off between keeping with future-proof logic in the code or remove it altogether and add it back if in the future we add support for vfio.

Sure, let's have the discussion. I'm pretty sure that there are things that we won't use whatsoever, e.g. ROM BAR, I/O type of BARs.

Also, I dislike the use of asserts in library code, which makes it more coupled with the code itself. I think error handling should be done in the binary crate. But this is a stylistic preference, I wouldn't block the CR on this right now. This will however hinder any upstreaming efforts in the future, if any.

I completely agree! Ultimately, I'd like to move all the logic that handles devices, the bus, MSI-X and corresponding configuration under vmm. When this is done the only thing left in the library portion would be definitions of constants and (maybe) some types. The ultimate goal would be to move that library under rust-vmm.

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Sure, let's have the discussion. I'm pretty sure that there are things that we won't use whatsoever, e.g. ROM BAR, I/O type of BARs.

I'm not sure how much of that is used in practice with modern devices (probably you're right that ROM and IO are not used), but the current vfio code handles all types of BARs: https://github.com/Manciukic/firecracker/blob/poc/pcie/src/pci/src/vfio.rs#L548

Ultimately, I'd like to move all the logic that handles devices, the bus, MSI-X and corresponding configuration under vmm.

gotcha!

PciDevice trait was defining (optional) methods to allocate and
deallocate BAR regions for devices. This logic is quite device specific
and when invoked we typically know what device it refers to exactly.
Currently, we only implement the allocate API for VirtIO devices (no
deallocation whatsoever).

Simplify things by dropping these APIs from the trait definition. Also,
remove the 32bit allocator argument from allocate_bars(); we always only
allocate a single 64-bit BAR for VirtIO devices.

Signed-off-by: Babis Chalios <bchalios@amazon.es>
In our case, only VirtIO PCI devices use a BAR region. Moreover, this
region has a fixed size and it's always a 64-bit region. This means we
don't handle 32-bit or IO BARs and we don't support a ROM bar. Encode
these assumptions to the logic that adds BAR regions and detects BAR
reprogramming attempts from the guest side so that we simplify the code.

Signed-off-by: Babis Chalios <bchalios@amazon.es>
Drop any ROM-related state we were holding in PciConfiguration and
ensure we are always returning a side of zero for the ROM BAR.

Signed-off-by: Babis Chalios <bchalios@amazon.es>
We only ever create type-0 (device) PCI configurations. The code that
was handling Bridge types was effectively dead code. Drop it.

Signed-off-by: Babis Chalios <bchalios@amazon.es>
Every time we were handling an MMIO write within a VirtIO device's BAR
we were logging a debug-level message when the write was not leading to
a device activation. This leads to way too verbose Firecracker logs up
until a device was set up properly. These logs don't really provide any
useful debugging information, so just drop it to keep logs readable.

Signed-off-by: Babis Chalios <bchalios@amazon.es>
@bchalios bchalios merged commit c28dbdb into firecracker-microvm:main Sep 16, 2025
6 of 7 checks passed
@bchalios bchalios deleted the pci_refactoring branch September 18, 2025 08:50
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