apply changes from upstream cl_ example projects to cl_firesim. also eliminate simulators that we dont use, so we dont have to maintain their scripts

Author: sagark

hdk/cl/developer_designs/cl_firesim/build/scripts/.critical_warnings

@@ -33,7 +33,7 @@ read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
 puts "AWS FPGA: Reading AWS Shell design";
 
 #Read AWS Design files
-read_verilog [ list \
+read_verilog -sv [ list \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v\
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv\
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v\

hdk/cl/developer_designs/cl_firesim/build/scripts/.warnings

@@ -34,12 +34,12 @@ else
   export C_TEST_NAME = $(C_SRC_DIR)/$(C_TEST).c
 endif
 
-export SIM_ROOT = $(CL_ROOT)/verif/sim
+export SIM_ROOT = $(CL_ROOT)/verif/sim/$(SIMULATOR)
 
 ifeq ($(C_TEST),test_null)
   export SIM_DIR = $(SIM_ROOT)/$(TEST)
 else
-  export SIM_DIR = $(SIM_ROOT)/$(C_TEST)
+  export SIM_DIR = $(SIM_ROOT)/$(C_TEST)_c
 endif
 
 

hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl

@@ -29,9 +29,14 @@ compile: $(COMPLIB_DIR)
 	cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64  +memcbk -licqueue -lca -v2005 -l compile.vcs.log
 
 run:
+
+ifeq ($(TEST),test_null)
+	cd $(SIM_DIR) && ./simv -l $(C_TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
+else
 	cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
+endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
-	cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl
-	cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
+	cd $(SIM_ROOT) && rm -rf create_libs.tcl

hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile

@@ -30,6 +30,9 @@ compile_chk:
 	cd $(SIM_DIR) && xelab -m64 -d ENABLE_PROTOCOL_CHK --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --timescale 1ps/1ps --debug typical --relax --mt 8 -L axi_protocol_checker_v1_1_12 -L axi_clock_converter_v2_1_11 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_12 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_11 -L axi_crossbar_v2_1_13 -L axi_dwidth_converter_v2_1_12 -L blk_mem_gen_v8_3_6 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_lib dpi --snapshot tb xil_defaultlib.tb xil_defaultlib.glbl xil_defaultlib.$(TEST)
 
 run:
-	cd $(SIM_DIR) && xsim -R -log test.log -tclbatch $(SCRIPTS_DIR)/waves.tcl tb
-
 
+ifeq ($(TEST),test_null)
+	cd $(SIM_DIR) && xsim -R -log $(C_TEST).log -tclbatch $(SCRIPTS_DIR)/waves.tcl tb
+else
+	cd $(SIM_DIR) && xsim -R -log $(TEST).log -tclbatch $(SCRIPTS_DIR)/waves.tcl tb
+endif