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sagarksagark
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xdc adds RAM_STYLE ULTRA property. currently hardcoded path
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‎hdk/cl/developer_designs/cl_firesim/build/constraints/cl_synth_user.xdc‎

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# This contains the CL specific constraints for synthesis at the CL level
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#get_cells firesim_top/top/SimpleNICWidget_0/incomingPCISdat/BRAMQueue/fq/ram*
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set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_0/incomingPCISdat/BRAMQueue/fq/ram_reg]
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set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_0/outgoingPCISdat/BRAMQueue/fq/ram_reg]

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